US-12628356-B2 - Multi-lateral recessed MIM structure

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

Inventors

• Alexander Kalnitsky
• Ru-Liang Lee
• Ming Chyi Liu
• Sheng-Chan Li
• Sheng-Chau Chen

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20230628

Claims (20)

1. 1 . An integrated chip, comprising: a dielectric stack disposed over a substrate and comprising a first plurality of layers interleaved between a second plurality of layers, wherein the dielectric stack has one or more surfaces that form a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers and wherein the plurality of indentations have depths that increase as a vertical distance from the substrate increases; and a capacitor structure lining the one or more surfaces of the dielectric stack, wherein the capacitor structure comprises conductive electrodes separated by a capacitor dielectric.
2. 2 . The integrated chip of claim 1 , wherein the capacitor structure has surfaces separated by a cavity, the cavity having a first width between sidewalls of a first layer of the first plurality of layers and a second width between sidewalls of a second layer of the second plurality of layers, the second width different than the first width.
3. 3 . The integrated chip of claim 2 , further comprising: a stopper continuously extending over the cavity and past sidewalls of the capacitor structure arranged along a top of the cavity.
4. 4 . The integrated chip of claim 2 , wherein one or more of the surfaces of the capacitor structure are angled at an acute angle measured through the cavity and with respect to a line extending along a bottom of a first one of the first plurality of layers.
5. 5 . The integrated chip of claim 2 , wherein the plurality of indentations respectively have a tapered height as viewed in a cross-sectional view, the tapered height decreasing as a lateral distance from a center of the cavity increases.
6. 6 . The integrated chip of claim 1 , wherein the first plurality of layers and the second plurality of layers comprise different silicate glasses.
7. 7 . The integrated chip of claim 1 , further comprising: an interconnect via extending through at least two of the first plurality of layers; and an interconnect wire contacting a top of the interconnect via and extending through at least two of the first plurality of layers.
8. 8 . The integrated chip of claim 1 , wherein the second plurality of layers comprise a first trapezoidal shaped segment disposed laterally between the capacitor structure and an additional capacitor structure and a second trapezoidal shaped segment disposed over the first trapezoidal shaped segment and laterally between the capacitor structure and the additional capacitor structure.
9. 9 . The integrated chip of claim 1 , wherein the plurality of indentations are formed by a curved surface of the dielectric stack; and wherein the dielectric stack comprises a substantially straight surface extending between vertically neighboring ones of the plurality of indentations.
10. 10 . The integrated chip of claim 1 , wherein one of the conductive electrodes continuously extends from within the dielectric stack to over a top surface of the dielectric stack.
11. 11 . An integrated chip, comprising: a dielectric stack disposed over a substrate and comprising a first plurality of layers of a first material interleaved between a second plurality of layers of a second material, wherein the dielectric stack comprises one or more surfaces defining a capacitor opening; a capacitor structure lining the one or more surfaces of the dielectric stack defining the capacitor opening, wherein the capacitor structure has a plurality of protrusions extending outward from a sidewall of the capacitor structure to a maximum extension defined by the second plurality of layers; and wherein the capacitor structure has interior surfaces defining a cavity separating the interior surfaces.
12. 12 . The integrated chip of claim 11 , wherein the capacitor structure comprises a first electrode separated from a second electrode by a capacitor dielectric.
13. 13 . The integrated chip of claim 12 , further comprising: a first upper interconnect disposed on an upper surface of the first electrode, the upper surface over a top of the dielectric stack; and a second upper interconnect disposed on an upper surface of the second electrode, the upper surface of the second electrode over the top of the dielectric stack.
14. 14 . The integrated chip of claim 11 , wherein the plurality of protrusions have a rounded profile as viewed along a cross-sectional view of the capacitor structure.
15. 15 . The integrated chip of claim 11 , further comprising: a lower inter-level dielectric (ILD) structure arranged between the dielectric stack and the substrate; and a lower interconnect disposed within the lower ILD structure below the capacitor structure.
16. 16 . The integrated chip of claim 15 , further comprising: an etch stop layer separating the lower ILD structure from the dielectric stack, wherein the capacitor structure extends through the etch stop layer to a bottom surface that contacts the lower interconnect.
17. 17 . The integrated chip of claim 11 , further comprising: a lower ILD structure arranged between the dielectric stack and the substrate; and an etch stop layer separating the lower ILD structure from the dielectric stack, wherein the capacitor structure is above an upper surface of the etch stop layer.
18. 18 . The integrated chip of claim 11 , further comprising: an interconnect wire extending through at least two of the first plurality of layers; a first interconnect via contacting the capacitor structure; and a second interconnect via contacting the interconnect wire, wherein the second interconnect via vertically extends below a bottom of the first interconnect via.
19. 19 . The integrated chip of claim 11 , further comprising: an interconnect via extending through at least two of the first plurality of layers; an interconnect wire disposed over the interconnect via and contacting the interconnect via along an interface; and wherein the capacitor structure extends from below the interface to above the interface.
20. 20 . An integrated chip, comprising: a dielectric stack disposed over a substrate and comprising a first plurality of layers interleaved between a second plurality of layers, wherein the dielectric stack has one or more surfaces that form a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers; a capacitor structure lining the one or more surfaces of the dielectric stack; wherein the first plurality of layers comprise a first layer having a first thickness directly over an upper surface of an immediately underlying one of the second plurality of layers and a second non-zero thickness laterally outside of the upper surface, the first thickness being larger than the second non-zero thickness; wherein the dielectric stack further comprises an etch stop layer disposed between adjacent ones of the first plurality of layers, the etch stop layer comprising a different material than both the first plurality of layers and the second plurality of layers; and wherein the capacitor structure vertically extends from below a bottom of the etch stop layer to above a top of the etch stop layer.

Description

REFERENCE TO RELATED APPLICATIONS This application is a Divisional of U.S. application Ser. No. 17/361,723, filed on Jun. 29, 2021, which claims the benefit of U.S. Provisional Application No. 63/157,045, filed on Mar. 5, 2021. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety. BACKGROUND Integrated chips are formed on semiconductor die comprising millions or billions of transistor devices. The transistor devices are configured to act as switches and/or to produce power gains so as to enable logical functionality for an integrated chip (e.g., form a processor configured to perform logic functions). Integrated chips also comprise passive devices, such as capacitors, resistors, inductors, varactors, etc. Passive devices are widely used to control integrated chip characteristics, such as gains, time constants, etc. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated chip having a MIM (metal-insulator-metal) capacitor structure disposed within a capacitor opening having a variable width that oscillates between smaller and larger widths over a height of the capacitor opening. FIG. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip having a MIM capacitor structure within a capacitor opening having a variable width. FIGS. 3A-3B illustrate cross-sectional views of some additional embodiments of integrated chips having MIM capacitor structures within capacitor openings having variable widths. FIG. 4 illustrates a cross-sectional view of some additional embodiments of an integrated chip having a MIM capacitor structure within a capacitor opening having a variable width. FIGS. 5A-5C illustrate cross-sectional views of some additional embodiments of integrated chips having a MIM capacitor structure within a capacitor opening having a variable width. FIGS. 6A-6B illustrate some embodiments of an image sensor integrated chip having a MIM capacitor structure within a capacitor opening having a variable width. FIG. 7 illustrates a cross-sectional view of some additional embodiments of an integrated chip having multiple MIM capacitor structures within a capacitor opening having a variable width. FIGS. 8A-8C illustrate some embodiments of integrated chips having MIM capacitor structures within capacitor openings having different shapes. FIGS. 9-20 illustrate cross-sectional views of some embodiments of a method of forming an integrated chip having a MIM capacitor structure within a capacitor opening having a variable width. FIG. 21 illustrates a flow diagram of some embodiments of a method of forming an integrated chip having a MIM capacitor structure within a capacitor opening having a variable width. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A MIM (metal-insulator-metal) capacitor is a passive device that is typically arranged within a back-end-of-the line (BEOL) interconnect stack of an integrated chip. A MIM capacitor may be fabricated by performing an isotrop