US-12628358-B2 - Vertically integrated device stack including system on chip and power management integrated circuit

Abstract

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Inventors

• Peng Zou
• Syrus Ziai

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260512

Application Date

20231206

Claims (20)

1. 1 . An integrated semiconductor device, comprising: a package substrate having a first surface, a second surface and a plurality of first via interconnects, wherein the package substrate is configured to be electrically coupled to a socket substrate via a plurality of electrical connectors, and the socket substrate has a third surface configured to face the second surface of the package substrate; a system-on-chip (SoC) die disposed on the first surface of the package substrate; and a power management integrated circuit (PMIC) die that is mechanically coupled to the second surface of the package substrate, wherein: the PMIC die is electrically coupled to the SOC die via the plurality of first via interconnects of the package substrate and configured to provide DC power to the SOC die via a plurality of DC connections electrically coupled to the plurality of first via interconnects of the package substrate; and the PMIC die includes a plurality of thin film inductors corresponding to the plurality of DC connections, and the plurality of thin film inductors is located adjacent to or facing the second surface of the package substrate, the plurality of thin film inductors having a height of less than 1.5 millimeters (mm) extending from the PMIC die towards the SoC die.
2. 2 . The integrated semiconductor device of claim 1 , wherein: each of the plurality of thin film inductors includes a respective conductive wire; at least two of the plurality of thin film inductors are electrically coupled to each other via the respective conductive wires; and the respective conductive wires of the at least two of the plurality of thin film inductors are electrically connected in series.
3. 3 . The integrated semiconductor device of claim 1 , wherein the SoC die is a flip-chip coupled onto the first surface of the package substrate and includes a plurality of signal inputs/outputs (I/Os) and a plurality of power connections.
4. 4 . The integrated semiconductor device of claim 3 , wherein: the plurality of power connections is located on a first region of the SoC die and aligned with the plurality of first via interconnects of the package substrate; and the plurality of power connections is electrically coupled to the plurality of DC connections of the PMIC die via the plurality of first via interconnects and configured to receive the DC power from the PMIC die.
5. 5 . The integrated semiconductor device of claim 4 , wherein: the plurality of signal I/Os is located on a second region of the SoC die and electrically coupled to a plurality of first interconnect wires of the package substrate; and each of the plurality of first interconnect wires is routed between two conductive contacts that are respectively located on the first and second surfaces of the package substrate, and electrically coupled to a respective one of the plurality of electrical connectors coupled between the package substrate and the socket substrate.
6. 6 . The integrated semiconductor device of claim 5 , wherein: the second region is distinct from the first region, such that the plurality of power connections are physically separated from the plurality of signal I/Os.
7. 7 . The integrated semiconductor device of claim 3 , further comprising a first interposer disposed between the SoC die and the first surface of the package substrate, wherein the first interposer further includes a plurality of second via interconnects configured to electrically couple the plurality of power connections and the plurality of signal I/Os of the SoC die to the package substrate.
8. 8 . The integrated semiconductor device of claim 7 , further comprising a second interposer disposed between the package substrate and the PMIC die, wherein the second interposer further includes a plurality of third via interconnects configured to electrically couple the plurality of power connections of the SoC die to the plurality of DC connections of the PMIC die.
9. 9 . The integrated semiconductor device of claim 1 , further comprising a plurality of output capacitors electrically coupled to the plurality of DC connections provided by the PMIC die, and the plurality of output capacitors is formed on one of the SoC die, the package substrate, and the PMIC die and has a capacitor footprint that substantially overlaps a first footprint of the SoC die or a second footprint of the PMIC die.
10. 10 . The integrated semiconductor device of claim 1 , wherein the PMIC die is configured to provide a first internal supply voltage and a ground to the SoC die via the plurality of DC connections of the PMIC die and the plurality of first via interconnects of the package substrate, further comprising: a plurality of first power rails that are physically separated from each other and electrically coupled to the first internal supply voltage; and a plurality of second power rails that are physically separated from each other and electrically coupled to the ground; wherein each of the plurality of first power rails and the plurality of second power rails is formed on one of the SoC die, the package substrate, and the PMIC die.
11. 11 . The integrated semiconductor device of claim 10 , further comprising a plurality of output capacitors electrically coupled to a first subset of the plurality of DC connections in the PMIC die to provide the first internal supply voltage, and the plurality of output capacitors is formed on the one of the SoC die, the package substrate, and the PMIC die where the plurality of first power rails and the plurality of second power rails are formed.
12. 12 . The integrated semiconductor device of claim 1 , wherein the PMIC die includes a power management interface and a plurality of DC-DC converters, and the PMIC die is configured to receive an input DC supply and outputs a plurality of internal supply voltages at the plurality of DC connections using the plurality of DC-DC converters.
13. 13 . The integrated semiconductor device of claim 12 , wherein one of the plurality of DC-DC converters includes one of the plurality of thin film inductors, and the one of the plurality of thin film inductors is electrically coupled to one of the plurality of DC connections.
14. 14 . The integrated semiconductor device of claim 12 , wherein the PMIC die is electrically coupled to a power source and configured to receive the input DC supply from the power source via one or more interconnect wires of the package substrate and a subset of the plurality of electrical connectors.
15. 15 . The integrated semiconductor device of claim 1 , further comprising the socket substrate, wherein the socket substrate includes a recessed portion formed on the third surface and configured to receive the PMIC die.
16. 16 . The integrated semiconductor device of claim 1 , further comprising the socket substrate, wherein the socket substrate includes a fourth surface opposing the third surface and a plurality of socket contacts formed on the fourth surface, and each of the plurality of electrical connectors is electrically coupled to a respective one of the plurality of socket contacts by one of a second interconnect wire or a through socket via.
17. 17 . The integrated semiconductor device of claim 1 , further comprising at least one of: a first electronic component disposed on the first surface of the package substrate and electrically coupled to the SoC die; and a second electronic component disposed on the second surface of the package substrate and electrically coupled to the PMIC die.
18. 18 . The integrated semiconductor device of claim 1 , wherein the SoC die is configured to sit on and faces away from the first surface of the package substrate, and wherein the SoC die includes a plurality of signal inputs/outputs (I/Os) and a plurality of power connections, and each of the plurality of signal I/Os and the plurality of power connections is electrically coupled to a conductive contact on the first surface of the package substrate via a bonding wire.
19. 19 . The integrated semiconductor device of claim 1 , further comprising a cover coupled to the first surface of the package substrate, wherein the cover is configured to conceal the SoC die and at least part of the first surface of the package substrate.
20. 20 . The integrated semiconductor device of claim 1 , wherein: each of the plurality of thin film inductors includes a respective conductive wire; at least two of the plurality of thin film inductors are electrically coupled to each other via the respective conductive wires; and the respective conductive wires of the at least two of the plurality of thin film inductors are electrically connected in parallel.

Description

RELATED APPLICATIONS This present application for patent is a Continuation of U.S. patent application Ser. No. 18/300,162, entitled “Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit” and filed on Apr. 13, 2023, which is a Continuation of U.S. patent application Ser. No. 17/096,828, entitled “Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit” and filed on Nov. 12, 2020, and claims the benefit of U.S. Provisional Patent Application No. 62/936,333, filed on Nov. 15, 2019 and entitled “Integrated System with Power Management Integrated Circuit Having On-Chip Thin Film Inductors,” and U.S. Provisional Patent Application No. 62/936,334, filed on Nov. 15, 2019 and entitled “Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit,” each of which is incorporated by reference in its entirety. BACKGROUND An electronic device oftentimes relies on a main logic board to connect a system on a chip (SoC) to a power management integrated circuit (PMIC), communication ports, external memory or storage, and other peripheral function modules. The SoC is implemented on an integrated circuit that integrates a microprocessor or central processing unit, memory, input/output ports and secondary storage on a single substrate. The PMIC is typically disposed adjacent to the SoC on the main logic board. The PMIC is physically and electrically coupled to the SoC via conductive wires formed in the main logic board to provide the SoC with direct current (DC) supply voltages via the conductive wires. However, as the conductive wires are routed on the main logic board, both parasitic effects (e.g., resistance, inductance and capacitance) and electrical noise are introduced at nodes connected to the DC supply voltages delivered by the conductive wires of the main logic board, thereby compromising performance of the SoC (e.g., voltage drop at a voltage supply, signal-to-noise ratio, speed of internal signals). As such, it would be highly desirable to provide a semiconductor device or system that reduces or suppresses parasitic effects and electrical noise coupled into the DC supply voltages provided to the SoC by the PMIC. SUMMARY Various embodiments of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description” one will understand how the aspects of various embodiments are used to provide a semiconductor device that integrates a system-on-chip (SoC) die and a power management integrated circuit (PMIC) die in a stack where the SoC die and the PMIC die are disposed adjacent to and on top of each other to reduce parasitic effects and electrical noise on the conductive wires that couple internal supply voltages provided by the PMIC die to the SoC die. In one aspect, an integrated semiconductor device includes at least the PMIC die, the SoC die, and a package substrate on which the PMIC die and the SoC die are mounted. The package substrate has a first surface, a second surface and a plurality of first via interconnects, and is configured to be electrically coupled to a socket substrate via a plurality of electrical connectors. The socket substrate has a third surface configured to face the second surface of the package substrate. The SoC die is disposed on the first surface of the package substrate, and the PMIC die is mechanically coupled to the second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via the plurality of first via interconnects of the package substrate, and is configured to provide DC power to the SOC die via a plurality of DC connections electrically coupled to the via interconnects of the package substrate. The PMIC die includes a plurality of thin film inductors corresponding to the plurality of DC connections, and the plurality of thin film inductors is located adjacent to or facing the second surface of the package substrate, e.g., between a top surface of the PMIC die and the second surface of the package substrate. Further, in another aspect of the invention, a semiconductor device includes a substrate having a surface and a thin film inductor that is formed on top of the surface of the substrate and has a conductive wire, a first stack of magnetic layers and a second stack of magnetic layers. The conductive wire is disposed between the first and second stacks of magnetic layers, and the thin film inductor is configured to provide a magnetic field in the first and second stacks of magnetic layers in response to a current passing through the conductive wire. The first stack of magnetic layers has a first edge portion extending in parallel with a longitudinal axis of