US-12628360-B2 - Semiconductor device with protective protrusion

US12628360B2US 12628360 B2US12628360 B2US 12628360B2US-12628360-B2

Abstract

A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

Inventors

Kazuya Kobayashi
Atsushi Kurokawa
Hiroaki Tokuya
Isao Obu
Yuichi Saito

Assignees

MURATA MANUFACTURING CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230821
Priority Date: 20180628

Claims (9)

1 . A semiconductor device comprising: a substrate; a target element to be protected arranged on the substrate; a protrusion arranged on the substrate; an insulating film arranged on the substrate and covering the target element and at least a side surface of the protrusion; and an electrode pad for external connection arranged on the insulating film, the electrode pad at least partially overlapping both the target element and the protrusion as seen in plan view, wherein a maximum distance between an uppermost surface of the protrusion and the electrode pad in a height direction is shorter than a maximum distance between an uppermost surface of the target element and the electrode pad in the height direction, and wherein the uppermost surface of the protrusion is connected to the electrode pad while the uppermost surface of the target element is not connected to the electrode pad.
2 . The semiconductor device according to claim 1 , further comprising an interconnection line arranged on the electrode, wherein the electrode pad is connected to the interconnection line.
3 . The semiconductor device according to claim 1 , further comprising a circuit element arranged on the substrate, the circuit element being a component of an electronic circuit, wherein the protrusion includes the circuit element therein.
4 . The semiconductor device according to claim 1 , wherein an upper surface of the insulating film is substantially flat.
5 . The semiconductor device according to claim 1 , wherein the protrusion is arranged on at least each of opposite sides of the target element as seen in plan view.
6 . The semiconductor device according to claim 1 , wherein the target element is a capacitor.
7 . The semiconductor device according to claim 1 , wherein the target element is a resistor.
8 . The semiconductor device according to claim 1 , wherein a side face of the protrusion is inclined.
9 . The semiconductor device according to claim 1 , wherein the protrusion is arranged on each of opposite sides of the target element.

Description

This application is a continuation of U.S. patent application Ser. No. 16/452,637 filed on Jun. 26, 2019, which claims priority from Japanese Patent Application No. 2018-122922 filed on Jun. 28, 2018, and claims priority from Japanese Patent Application No. 2019-056771 filed on Mar. 25, 2019. The content of these applications are incorporated herein by reference in their entireties. BACKGROUND The present disclosure relates to semiconductor devices. A semiconductor device having a pad-on-element (PoE) structure, in which a pad is arranged immediately above an element, such as a transistor, to reduce the size of a semiconductor chip is publicly known (for example, Japanese Unexamined Patent Application Publication No. 2004-311787 (hereinafter referred to as Patent Document 1)). In the semiconductor device disclosed in Patent Document 1, a stripe-shaped interconnection line is disposed below the pad, and therefore the pad has asperities on its surface. The surface asperities of the pad are formed in order to extend an area on which an external stress acts on at the time of, for example, bonding and to relieve the external stress. BRIEF SUMMARY Even in the case where the pad has surface asperities and the area on which the external stress acts on is extended, when the circuit element arranged directly under the pad is subjected to the stress, the circuit element may be damaged. The present disclosure provides a semiconductor device capable of reducing damage to a circuit element directly under an electrode pad caused by impact exerted on the electrode pad. According to embodiments of the present disclosure, a semiconductor device includes a substrate, a target element to be protected, a protrusion, an insulating film, and an electrode pad for external connection. The target element is arranged on the substrate. The protrusion is arranged on the substrate. The insulating film is arranged on the substrate and covers the target element and at least a side surface of the protrusion. The electrode pad is arranged on the insulating film and at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between an upper surface of the protrusion and the electrode pad in a height direction is shorter than or equal to a maximum distance between an upper surface of the target element and the electrode pad in the height direction. When an impact load is exerted on the electrode pad, it propagates through the insulating film to the target element and the protrusion positioned below. Because the impact load is distributed to the target element and the protrusion, the damage to the target element can be reduced. Other features, elements, characteristics and advantages of the present disclosure will become more apparent from the following detailed description of embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS FIG. 1A is a plan view of a semiconductor device according to a first embodiment, and FIG. 1B is a cross-sectional view taken along a dot-and-dash line 1B-1B in FIG. 1A; FIGS. 2A and 2B are cross-sectional views of semiconductor devices according to variations of the first embodiment; FIG. 3A is a cross-sectional view of a semiconductor device according to a second embodiment, FIG. 3B is an equivalent circuit diagram of a portion of an electronic circuit mounted on a substrate, and FIG. 3C is a cross-sectional view of a semiconductor device according to a variation of the second embodiment; FIGS. 4A and 4B are cross-sectional views of semiconductor devices according to other variations of the second embodiment; FIG. 5 is a cross-sectional view of a semiconductor device according to still another variation of the second embodiment; FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment; FIG. 7A is a cross-sectional view of a semiconductor device according to a fourth embodiment, and FIG. 7B is a cross-sectional view of a semiconductor device according to a variation of the fourth embodiment; FIG. 8A is a cross-sectional view of a semiconductor device according to a fifth embodiment, and FIGS. 8B and 8C are cross-sectional views of semiconductor devices according to variations of the fifth embodiment; FIG. 9A is a cross-sectional view of a semiconductor device according to a sixth embodiment, and FIGS. 9B and 9C are cross-sectional views of semiconductor devices according to variations of the sixth embodiment; FIG. 10A is a plan view of a semiconductor device according to a seventh embodiment, and FIG. 10B is a cross-sectional view taken along a dot-and-dash line 10B-10B in FIG. 10A; FIGS. 11A, 11B, and 11C are plan views of semiconductor devices according to variations of the seventh embodiment; FIGS. 12A and 12B are plan views of semiconductor devices according to variations of the seventh embodiment; and FIG. 13A is a cross-sectional view of a semiconducto