US-12628365-B2 - Semiconductor device structure and methods of forming the same

Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first plurality of vertically aligned semiconductor layers disposed over a substrate and a first gate electrode layer surrounding each of the first plurality of vertically aligned semiconductor layers. The first gate electrode layer includes first one or more work function metal layers disposed between adjacent semiconductor layers of the first plurality of vertically aligned semiconductor layers and two first conductive layers disposed on opposite sides of the first one or more work function metal layers. The first conductive layers include a material different from the first one or more work function metal layers. The first gate electrode layer further includes a second conductive layer disposed on the first conductive layers, and the second conductive layer and the first conductive layers include a same material.

Inventors

• CHENG-WEI CHANG
• Shahaji B. More
• Chi-Yu Chou
• Yueh-Ching Pai

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20220721

Claims (20)

1. 1 . A method for forming a semiconductor device structure, comprising: forming first and second fins from a substrate, wherein the first fin includes a first plurality of semiconductor layers and the second fin includes a second plurality of semiconductor layers; depositing a gate dielectric layer around the first plurality of semiconductor layers, wherein the gate dielectric layer has an outer surface; depositing first one or more work function metal layers between adjacent semiconductor layers of the first plurality of semiconductor layers; recessing the first one or more work function metal layers, wherein an edge surface of the first one or more work function metal layers is recessed from the outer surface of the gate dielectric layer; depositing second one or more work function metal layers between adjacent semiconductor layers of the second plurality of semiconductor layers; recessing the second one or more work function metal layers; selectively forming first conductive layers on opposite sides of the first one or more work function metal layers and on opposite sides of the second one or more work function metal layers; and forming a second conductive layer on the first conductive layers.
2. 2 . The method of claim 1 , further comprising forming a first dielectric material between one of the first conductive layers in contact with the first one or more work function metal layers and one of the first conductive layers in contact with the second one or more work function metal layers prior to forming the second conductive layer.
3. 3 . The method of claim 2 , further comprising forming a second dielectric material in the second conductive layer, wherein the second dielectric material is in contact with the first dielectric material.
4. 4 . The method of claim 3 , further comprising forming a liner between the first and second fins.
5. 5 . The method of claim 4 , further comprising removing vertical portions of the liner, wherein a horizontal portion of the liner remains.
6. 6 . A method for forming a semiconductor device structure, comprising: forming first and second fins from a substrate, wherein the first fin includes a first plurality of semiconductor layers and the second fin includes a second plurality of semiconductor layers; forming a dielectric feature between the first and second fins; forming a sacrificial gate electrode layer above the first and second fins and the dielectric feature; performing a planarization process to expose the dielectric feature; removing the dielectric feature; removing the sacrificial gate electrode layer; depositing a gate dielectric layer around the first plurality of semiconductor layers, wherein the gate dielectric layer has an outer surface; depositing first one or more work function metal layers between adjacent semiconductor layers of the first plurality of semiconductor layers; recessing the first one or more work function metal layers, wherein an edge surface of the first one or more work function metal layers is recessed from the outer surface of the gate dielectric layer; and selectively forming first conductive layers on opposite sides of the first one or more work function metal layers.
7. 7 . The method of claim 6 , wherein the first fin comprises a first sacrificial layer disposed over the first plurality of semiconductor layers.
8. 8 . The method of claim 7 , wherein the dielectric feature comprises a liner and a second sacrificial layer disposed on the liner.
9. 9 . The method of claim 8 , wherein a top surface of the first sacrificial layer and a top surface of the second sacrificial layer are coplanar.
10. 10 . The method of claim 9 , further comprising removing the first sacrificial layer.
11. 11 . The method of claim 6 , further comprising forming a first mask around the second plurality of semiconductor layers prior to the depositing of the first one or more work function metal layers.
12. 12 . The method of claim 11 , further comprising removing the first mask after the depositing of the first one or more work function metal layers.
13. 13 . The method of claim 12 , further comprising depositing a second mask around the first plurality of semiconductor layers and the first one or more work function metal layers.
14. 14 . The method of claim 13 , further comprising depositing second one or more work function metal layers between adjacent semiconductor layers of the second plurality of semiconductor layers.
15. 15 . The method of claim 14 , further comprising selectively depositing second conductive layers on opposite sides of the second one or more work function metal layers.
16. 16 . The method of claim 15 , wherein the first and second conductive layers are selectively deposited at a same time.
17. 17 . A method for forming a semiconductor device structure, comprising: forming a fin from a substrate, wherein the fin includes a plurality of semiconductor layers; forming a sacrificial layer adjacent the fin; forming a sacrificial gate stack above a first portion of the fin and a first portion of the sacrificial layer; depositing a spacer around the sacrificial gate stack, on a second portion of the fin, and on a second portion of the sacrificial layer; removing portions of the spacer formed on horizontal surfaces; forming source/drain epitaxial features adjacent the second portion of the sacrificial layer; then removing the sacrificial layer; depositing a first dielectric material adjacent the source/drain epitaxial feature; and depositing a second dielectric material on the first dielectric material, wherein the second dielectric material is adjacent the spacer.
18. 18 . The method of claim 17 , further comprising depositing one or more work function metal layers between adjacent semiconductor layers of the plurality of semiconductor layers.
19. 19 . The method of claim 18 , further comprising selectively depositing first conductive layers on opposite sides of the one or more work function metal layers, wherein the first dielectric material is deposited adjacent the first conductive layer.
20. 20 . The method of claim 19 , further comprising depositing a second conductive layer on the first conductive layers and the first dielectric material, wherein the second dielectric material is formed through the second conductive layer.

Description

BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. Therefore, there is a need to improve processing and manufacturing ICs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-4 are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. FIGS. 5A and 5B are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of FIG. 4, in accordance with some embodiments. FIGS. 6A-10A are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of FIG. 4, in accordance with some embodiments. FIGS. 6B-10B are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line B-B of FIG. 4, in accordance with some embodiments. FIG. 11 is a top view of the semiconductor device structure of FIGS. 10A and 10B, in accordance with some embodiments. FIGS. 12A-17A are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of FIG. 11, in accordance with some embodiments. FIGS. 12B-17B are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line B-B of FIG. 11, in accordance with some embodiments. FIGS. 12C-17C are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line C-C of FIG. 11, in accordance with some embodiments. FIGS. 18A-18H are cross-sectional views of various stages of manufacturing the semiconductor device structure, in accordance with some embodiments. FIGS. 19A and 19B are cross-sectional side views of one of various stages of manufacturing the semiconductor device structure taken along lines A-A, B-B of FIG. 11, respectively, in accordance with some embodiments. FIG. 20 is a cross-sectional view of one of various stages of manufacturing the semiconductor device structure, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. FIGS. 1-20 show exemplary sequential processes for manufacturing a semiconductor device structure 100, in accordance with some embodiments. It is understood that additional operations can be provided before, during, and after processes shown by FIGS. 1-20 and some of the oper