US-12628366-B2 - Semiconductor device and method for fabricating the same

US12628366B2US 12628366 B2US12628366 B2US 12628366B2US-12628366-B2

Abstract

A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.

Inventors

Chih-Wei Yang
Ssu-I Fu
Chih-Kai Hsu
Chun-Hsien Lin

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260512
Application Date: 20230203
Priority Date: 20221219

Claims (14)

1 . A method for fabricating a semiconductor device, comprising: providing a substrate having a high-voltage (HV) region, a low-voltage (LV) region, and a dummy region between the HV region and the LV region; forming a HV device on the HV region, wherein the HV device comprises: a first gate structure on the substrate; and a first epitaxial layer adjacent to the first gate structure, wherein a top surface of the first epitaxial layer comprises a first V-shape; forming a LV device on the LV region, wherein the LV device comprises: a second gate structure on the substrate; and a second epitaxial layer adjacent to the second gate structure, wherein a top surface of the second epitaxial layer comprises a first planar surface; and forming a dummy device on the dummy region, wherein the dummy region comprises a ring shape around the LV region.
2 . The method of claim 1 , wherein the first epitaxial layer comprises: a first inclined sidewall; a second inclined sidewall; and a second planar surface connecting the first inclined sidewall and the second inclined sidewall.
3 . The method of claim 2 , wherein the second planar surface is lower than the first planar surface.
4 . The method of claim 1 , wherein the substrate comprises a medium-voltage (MV) region, the method comprising: forming a MV device on the MV region, wherein the MV device comprises: a third gate structure on the substrate; and a third epitaxial layer adjacent to the third gate structure, wherein a top surface of the third epitaxial layer comprises a second V-shape.
5 . The method of claim 4 , wherein the third epitaxial layer comprises: a third inclined sidewall; a fourth inclined sidewall; and a third planar surface connecting the third inclined sidewall and the fourth inclined sidewall.
6 . The method of claim 5 , wherein the third planar surface is lower than the first planar surface.
7 . The method of claim 1 , wherein the substrate comprises the dummy region between the HV region and the LV region, the method comprising: forming the dummy device on the dummy region, wherein the dummy device comprises: a fourth gate structure on the substrate; and a fourth epitaxial layer adjacent to the fourth gate structure.
8 . A semiconductor device, comprising: a substrate having a high-voltage (HV) region, a low-voltage (LV) region, and a dummy region between the HV region and the LV region; a HV device on the HV region, wherein the HV device comprises: a first gate structure on the substrate; and a first epitaxial layer adjacent to the first gate structure, wherein a top surface of the first epitaxial layer comprises a V-shape; a LV device on the LV region, wherein the LV device comprises: a second gate structure on the substrate; and a second epitaxial layer adjacent to the second gate structure, wherein a top surface of the second epitaxial layer comprises a first planar surface; and a dummy device on the dummy region, wherein the dummy device comprises: a fourth gate structure on the substrate; and a fourth epitaxial layer adjacent to the fourth gate structure.
9 . The semiconductor device of claim 8 , wherein the first epitaxial layer comprises: a first inclined sidewall; a second inclined sidewall; and a second planar surface connecting the first inclined sidewall and the second inclined sidewall.
10 . The semiconductor device of claim 9 , wherein the second planar surface is lower than the first planar surface.
11 . The semiconductor device of claim 8 , wherein the substrate comprises a medium-voltage (MV) region, the method comprising: a MV device on the MV region, wherein the MV device comprises: a third gate structure on the substrate; and a third epitaxial layer adjacent to the third gate structure, wherein a top surface of the third epitaxial layer comprises a second V-shape.
12 . The semiconductor device of claim 11 , wherein the third epitaxial layer comprises: a third inclined sidewall; a fourth inclined sidewall; and a third planar surface connecting the third inclined sidewall and the fourth inclined sidewall.
13 . The semiconductor device of claim 12 , wherein the third planar surface is lower than the first planar surface.
14 . The semiconductor device of claim 8 , wherein the dummy region comprises a ring shape around the LV region.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a method of fabricating semiconductor device, and more particularly to a method of integrating high-voltage (HV) device, medium-voltage (MV) device, and low-voltage (LV) device. 2. Description of the Prior Art In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffusion MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance. Moreover with the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate. However as the scale of current devices continue to decrease the integration of high-voltage devices and FinFET devices start to face numerous challenges such as current leakage and control of breakdown voltage. Hence, how to improve the current fabrication for improving performance of the device has become an important task in this field. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface. According to another aspect of the present invention, a semiconductor device includes a substrate having a high-voltage (HV) region and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer comprises a first planar surface. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-11 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. FIGS. 12-13 illustrate enlarged views of using selective epitaxial growth process to form epitaxial layers on the HV region, the MV region, the dummy region, and the LV region according to an embodiment of the present invention. DETAILED DESCRIPTION Referring to FIGS. 1-11, FIGS. 1-11 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention, in which FIG. 1 illustrates a top view for fabricating the semiconductor device according to an embodiment of the present invention and FIGS. 2-11 illustrate cross-section views for fabricating the semiconductor device along the sectional lines AA′, BB′, and CC′. As shown in FIGS. 1-2, a substrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided and three or more transistor regions including a high voltage (HV) region 14, a medium-voltage (MV) region 16, and a low-voltage (LV) region 18 are defined on the substrate 12, in which at least a HV device 114 is disposed on the HV region 14, a MV device 116 is disposed on the MV region 16, the LV region 18 could further