US-12628367-B2 - Vertical transistors having improved control of parasitic capacitance and gate-to-contact short circuits

Abstract

Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC. The fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region.

Inventors

• ChoongHyun Lee
• Ardasheir Rahman
• Xin Miao
• Brent A. Anderson
• Alexander Reznicek

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20211111

Claims (20)

1. 1 . A method of forming an integrated circuit (IC), the method comprising performing fabrication operations that form the IC, wherein the fabrication operations comprise: forming a channel fin; forming a gate structure along a sidewall surface of the channel fin; wherein the gate structure comprises a conductive gate having an L-shape profile; wherein the L-shape profile comprises a conductive gate leg region and a conductive gate foot region, the conductive gate foot region comprising a conductive gate foot region top surface extending over an entirety of the conductive gate foot region and intersecting a sidewall of the conductive gate leg region; forming a protective liner along the sidewall of the conductive gate leg region, such that an entirety of a bottom surface of the protective liner extends over an entirety of the conductive gate foot region top surface; and replacing the entirety of the conductive gate foot region with a dielectric foot region such that a space that was occupied by the conductive gate foot region is occupied by the dielectric foot region; wherein at least a portion of the space that was occupied by the conductive gate foot region is defined by a portion of the protective liner and a portion of the conductive gate leg region.
2. 2 . The method of claim 1 , wherein the conductive gate leg region is along the sidewall surface of the channel fin.
3. 3 . The method of claim 1 , wherein the conductive gate comprises a work function metal.
4. 4 . The method of claim 1 , wherein the dielectric foot region is non-sacrificial in that the dielectric foot region is present in a final version of the IC.
5. 5 . The method of claim 3 , wherein the work function metal comprises a p-type work function metal or an n-type work function metal.
6. 6 . The method of claim 2 , wherein the fabrication operations further comprise: forming a bottom source or drain (S/D) region communicatively coupled to a bottom end region of the channel fin; and forming a bottom S/D contact communicatively coupled to the bottom S/D region; wherein the dielectric foot region is between a portion of the conductive gate leg and a portion of the bottom S/D contact.
7. 7 . A method of forming an integrated circuit (IC), the method comprising performing fabrication operations that form the IC, wherein the fabrication operations comprise: forming a first channel fin; forming a second channel fin; forming a first gate structure along a sidewall surface of the first channel fin; wherein the first gate structure comprises a first conductive gate having a first L-shape profile; wherein the first L-shape profile comprises a first conductive gate leg region and a first conductive gate foot region, the first conductive gate foot region comprising a first conductive gate foot region top surface extending over an entirety of the first conductive gate foot region and intersecting a sidewall of the first conductive gate leg region; forming a first protective liner along the sidewall of the first conductive gate leg region, such that an entirety of a bottom surface of the first protective liner extends over an entirety of the first conductive gate foot region top surface; forming a second gate structure along a sidewall surface of the second channel fin; wherein the second gate structure comprises a second conductive gate having a second L-shape profile; wherein the second L-shape profile comprises a second conductive gate leg region and a second conductive gate foot region, the second conductive gate foot region comprising a second conductive gate foot region top surface extending over an entirety of the second conductive gate foot region and intersecting a sidewall of the second conductive gate leg region; forming a second protective liner along the sidewall of the second conductive gate leg region, such that an entirety of a bottom surface of the second protective liner extends over an entirety of the second conductive gate foot region top surface; replacing the entirety of the first conductive gate foot region with a first dielectric foot region such that a space that was occupied by the first conductive gate foot region is occupied by the first dielectric foot region; wherein at least a portion of the space that was occupied by the first conductive gate foot region is defined by a portion of the first protective liner and a portion of the first conductive gate leg region; and replacing the entirety of the second conductive gate foot region with a second dielectric foot region such that a space that was occupied by the second conductive gate foot region is occupied by the second dielectric foot region; wherein at least a portion of the space that was occupied by the second conductive gate foot region is defined by a portion of the second protective liner and a portion of the second conductive gate leg region.
8. 8 . The method of claim 7 , wherein: the first conductive gate leg region is along the sidewall surface of the first channel fin; and the second conductive gate leg region is along the sidewall surface of the second channel fin.
9. 9 . The method of claim 7 , wherein the first conductive gate and the second conductive gate comprise a work function metal.
10. 10 . The method of claim 7 , wherein the first dielectric foot region and the second dielectric foot region are non-sacrificial in that the first dielectric foot region and the second dielectric foot region are present in a final version of the IC.
11. 11 . The method of claim 9 , wherein the work function metal comprises a p-type work function metal or an n-type work function metal.
12. 12 . The method of claim 8 , wherein a portion of the first dielectric foot region and a portion of the second dielectric foot region are between a bottom region of the first conductive gate leg region and a bottom region of the second conductive gate leg region.
13. 13 . The method of claim 8 , wherein the fabrication operations further comprise: forming a shared bottom source or drain (S/D) region communicatively coupled to a bottom end region of the first channel fin and a bottom end region of the second channel fin; and forming a bottom S/D contact communicatively coupled to the shared bottom S/D region; wherein the first dielectric foot region and the second dielectric foot region are between: a portion of the first conductive gate leg and a portion of the shared bottom S/D contact; and a portion of the second conductive gate leg and the portion of the shared bottom S/D contact.
14. 14 . An integrated circuit (IC) comprising: a first channel fin; and a first gate structure along a sidewall surface of the first channel fin; wherein the first gate structure comprises a first conductive gate having a first L-shape profile; wherein the first L-shape profile comprises a first conductive gate leg region and a first dielectric foot region, the first dielectric foot region comprising a first dielectric foot region top surface extending over an entirety of the first dielectric foot region and intersecting a sidewall of the first conductive gate leg region; and a first protective liner along the sidewall of the first conductive gate leg region, such that an entirety of a bottom surface of the first protective liner extends over an entirety of the first dielectric foot region top surface; wherein a space occupied by the first dielectric foot region was previously occupied by a removed first conductive gate foot region; and wherein at least a portion of the space that was occupied by the removed first conductive gate foot region is defined by a portion of the first protective liner and a portion of the first conductive gate leg region.
15. 15 . The IC of claim 14 further comprising: a second channel fin; and a second gate structure along a sidewall surface of the second channel fin; wherein the second gate structure comprises a second conductive gate having a second L-shape profile; wherein the second L-shape profile comprises a second conductive gate leg region and a second dielectric foot region, the second dielectric foot region comprising a second dielectric foot region top surface extending over an entirety of the second dielectric foot region and intersecting a sidewall of the second conductive gate leg region; and a second protective liner along the sidewall of the second conductive gate leg region, such that an entirety of a bottom surface of the second protective liner extends over an entirety of the second dielectric foot region top surface; wherein a space occupied by the second dielectric foot region was previously occupied by a removed second conductive gate foot region; and wherein at least a portion of the space that was occupied by the removed second conductive gate foot region is defined by at portion of the second protective liner and a portion of the second conductive gate leg region.
16. 16 . The IC of claim 15 , wherein the first conductive gate and the second conductive gate comprise a work function metal.
17. 17 . The IC of claim 15 , wherein the first dielectric foot region and the second dielectric foot region are non-sacrificial in that the first dielectric foot region and the second dielectric foot region are present in a final version of the IC.
18. 18 . The IC of claim 16 , wherein the work function metal comprises a p-type work function metal or an n-type work function metal.
19. 19 . The IC of claim 15 , wherein a portion of the first dielectric foot region and a portion of the second dielectric foot region are between a bottom region of the first conductive gate leg region and a bottom region of the second conductive gate leg region.
20. 20 . The IC of claim 15 further comprising: a shared bottom source or drain (S/D) region communicatively coupled to a bottom end region of the first channel fin and a bottom end region of the second channel fin; and a bottom S/D contact communicatively coupled to the shared bottom S/D region; wherein the first dielectric foot region and the second dielectric foot region are between: a portion of the first conductive gate leg and a portion of the shared bottom S/D contact; and a portion of the second conductive gate leg and the portion of the shared bottom S/D contact.

Description

BACKGROUND The present invention relates in general to semiconductor devices and their fabrication. More specifically, the present invention relates to improved fabrication methodologies and resulting structures for vertical-transport field effect transistors (VTFETs) configured and arranged to provide improved control over parasitic capacitance (e.g., gate-to-gate, gate-to-source, gate-to-drain, etc.), as well as improved control over electrical short circuits that can occur between the VTFET gate and a bottom source or drain (S/D) contact formed in a relatively small spaces. Semiconductor devices are typically formed using active regions of a wafer. In an integrated circuit (IC) having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by incorporating n-type or p-type impurities in the layer of semiconductor material. A conventional MOSFET geometry is known as a planar device geometry in which the various parts of the MOSFET are laid down as planes or layers. Another type of MOSFET geometry is a non-planar FET known generally as a VTFET. VTFETs employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral/planar devices. In VTFETs, the source-to-drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VTFET configuration a major substrate surface is horizontal, and a vertical fin extends upward from the substrate surface. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the fin sidewalls. SUMMARY Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC, wherein the fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region. Embodiments of the invention are directed to a method of forming an IC. The method includes performing fabrication operations that form the IC. The fabrication operations include forming a first channel fin. A second channel fin is formed. A first gate structure is formed along a sidewall surface of the first channel fin, wherein the first gate structure includes a first conductive gate having a first L-shape profile, and wherein the first L-shape profile includes a first conductive gate foot region. A second gate structure is formed along a sidewall surface of the second channel fin, wherein the second gate structure includes a second conductive gate having a second L-shape profile, and wherein the second L-shape profile includes a second conductive gate foot region. The first conductive gate foot region is replaced with a first dielectric foot region. The second conductive gate foot region is replaced with a second dielectric foot region. Embodiments of the invention are directed to an IC that includes a first channel fin. A first gate structure is along a sidewall surface of the first channel fin. The first gate structure includes a first conductive gate having a first L-shape profile. The first L-shape profile includes a first conductive gate leg region and a first dielectric foot region. Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein. For a better understanding, refer to the description and to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS The subject matter which is regarded as the present invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 depicts two-dimensional (2D) cross-sectional views of a portion of an IC having VTFETs formed thereon in accordance with embodiments of the invention; and FIGS. 2-11 depict 2D cross-sectional view(s) of the IC shown in FIG. 1 after fabrication operations in accordance with aspects of the invention, in which: FIG. 2 depicts 2D cross-sectional views of an IC after fabrication operations according to embodiments of the invention; FIG. 3 depicts 2D cross-sectional views of an IC after fabrication operations according to embodiments of the invention; FIG. 4 depicts 2D cross-sectional views of an IC after fabrication operations according to embodiments of the invention; FIG. 5 depicts 2