US-12628369-B2 - Nitride-based semiconductor device with gate protection layer and method for manufacturing the same

Abstract

A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.

Inventors

• Liuchang MENG
• Hung-Yu Chen
• Kaiming FAN

Assignees

• INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.

Dates

Publication Date

20260512

Application Date

20210611

Claims (20)

1. 1 . A nitride-based semiconductor device, comprising: a first nitride-based semiconductor layer; a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer; two or more source/drain (S/D) electrodes disposed above the second nitride-based semiconductor layer; a gate electrode disposed above the second nitride-based semiconductor layer and between the S/D electrodes; a doped III-V semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode; a gate protection layer capping the gate electrode and the doped III-V semiconductor layer and separated from the S/D electrodes; and a first passivation layer covering the second nitride-based semiconductor layer and the gate protection layer and abutting against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer, wherein at least one material of the gate protection layer has an intrinsic stress selected to redistribute a stress from the first passivation layer, wherein a top surface of the second nitride-based semiconductor layer has a first region in contact with the gate protection layer and a second region in contact with the first passivation layer, an orthographic projection of the gate electrode on the second nitride-based semiconductor layer is free from overlapping with each of the first region and the second region, the gate electrode comprises a metal element, and a number per unit area of the metal element distributed on the second region is less than a number per unit area of the metal element distributed on the first region.
2. 2 . The semiconductor device of claim 1 , wherein the gate electrode comprises titanium nitride, and the metal element is titanium.
3. 3 . The semiconductor device of claim 1 , wherein the doped III-V semiconductor layer is entirely separated from the first passivation layer by the gate protection layer.
4. 4 . The semiconductor device of claim 1 , wherein the gate electrode is entirely separated from the first passivation layer by the gate protection layer.
5. 5 . The semiconductor device of claim 1 , wherein the doped III-V semiconductor layer has a pair of opposite sidewalls, and the gate protection layer at least extends from one of the sidewalls of the doped III-V semiconductor layer to another one of the sidewalls of the doped III-V semiconductor layer.
6. 6 . The semiconductor device of claim 5 , wherein the sidewalls of the doped III-V semiconductor layer are entirely covered by the gate protection layer.
7. 7 . The semiconductor device of claim 1 , wherein the gate electrode has a pair of opposite sidewalls, and the gate protection layer at least extends from one of the sidewalls of the gate electrode to another one of the sidewalls of the gate electrode.
8. 8 . The semiconductor device of claim 7 , wherein the gate electrode has a top surface between the sidewalls thereof, and the gate protection layer extends with covering the top surface of the gate electrode.
9. 9 . The semiconductor device of claim 7 , wherein the sidewalls of gate electrode are entirely covered by the gate protection layer.
10. 10 . The semiconductor device of claim 1 , wherein the gate protection layer comprises a first sidewall and a second sidewall that are opposite to each other, a distance from a sidewall of the doped III-V semiconductor layer facing one of the first sidewall and the second sidewall to the one of the first sidewall and the second sidewall is a first distance, a distance from a sidewall of the gate electrode facing the one of the first sidewall and the second sidewall to the one of the first sidewall and the second sidewall is a second distance, and the first distance is less than the second distance.
11. 11 . The semiconductor device of claim 10 , wherein a horizontal distance between a bottom end of the sidewall of the gate electrode facing the second nitride-based semiconductor layer and a top end of the sidewall of the doped III-V semiconductor layer away from the second nitride-based semiconductor layer is a third distance, a horizontal distance between a bottom end of the sidewall of the doped III-V semiconductor layer facing the second nitride-based semiconductor layer and a bottom end of the one of the first sidewall and the second sidewall of the gate protection layer facing the second nitride-based semiconductor layer is a fourth distance, and the third distance is greater than the fourth distance.
12. 12 . The semiconductor device of claim 1 , wherein the first passivation layer has a portion between the gate protection layer and the S/D electrode and in contact with the second nitride-based semiconductor layer.
13. 13 . The semiconductor device of claim 1 , further comprising: a second passivation layer disposed on the first passivation layer; and a field plate disposed on the second passivation extending from one of S/D electrodes to a position immediately on the gate protection layer.
14. 14 . The semiconductor device of claim 1 , wherein the gate protection layer is an oxide dielectric layer.
15. 15 . The semiconductor device of claim 1 , wherein the first passivation layer is a nitride-based dielectric layer.
16. 16 . A method for manufacturing the semiconductor device of claim 1 , comprising: forming the first nitride-based semiconductor layer disposed over a substrate; forming the second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming the gate electrode over the second nitride-based semiconductor layer by depositing the metal element and a group V element; forming the gate protection layer covering the gate electrode; cleaning the second region of the second nitride-based semiconductor layer which is free from the coverage of the gate protection layer using a standard cleaning solution; and forming a passivation layer covering the gate protection layer and the second region of the second nitride-based semiconductor layer.
17. 17 . The method of claim 16 , further comprising: removing a portion of the passivation layer to form an opening exposing the second nitride-based semiconductor layer; and forming the source/drain (S/D) electrode in the opening of the second nitride-based semiconductor layer.
18. 18 . The method of claim 16 , wherein the standard clean solution is a mixture of HCl, H 2 O 2 , and H 2 O.
19. 19 . The method of claim 16 , wherein cleaning the second region of the second nitride-based semiconductor layer is performed such that the metal element accumulated at a top surface of the second nitride-based semiconductor layer is removed.
20. 20 . The method of claim 19 , the gate electrode comprises titanium nitride, and the metal element includes titanium.

Description

FIELD OF THE DISCLOSURE The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a gate protection layer located between the gate electrode and the passivation layer for improving electrical characteristics of the semiconductor device. BACKGROUND OF THE DISCLOSURE In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT), heterojunction field effect transistor (HFET), and modulation-doped FETs (MODFET). During manufacturing of III-nitride devices, unwanted processing residue may remain, impairing the quality of the final device. Further, stresses from various passivation layers may negatively impact the semiconductor device. Therefore, improvements in manufacturing techniques and layer structures is needed to improve device yield and performance. SUMMARY OF THE DISCLOSURE In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The S/D electrodes are disposed above the second nitride-based semiconductor layer. The gate electrode is disposed above the second nitride-based semiconductor layer and between the S/D electrodes. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer. At least one material of the gate protection layer has an intrinsic stress selected to redistribute a stress from the passivation layer. In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed on a substrate. A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. A gate electrode is formed over the second nitride-based semiconductor layer by depositing a metal element and a group V element. A gate protection layer is formed to cover the gate electrode. An area of the second nitride-based semiconductor layer which is free from the coverage of the gate protection layer is cleaned by using a standard cleaning solution. A passivation layer covering the gate protection layer and the area of the second nitride-based semiconductor layer is formed. In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped III-V semiconductor layer, a gate electrode, a gate protection layer and a passivation layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer. The doped III-V semiconductor layer is disposed above the second nitride-based semiconductor layer. The gate electrode is disposed above the doped III-V semiconductor layer and has an edge spaced apart from an edge of the doped III-V semiconductor layer by a first distance. The gate protection layer covers the gate electrode and the doped III-V semiconductor layer and has an edge separated from the edge of the doped III-V semiconductor layer by a second distance. The second distance is less than the first distance. The passivation layer covers the second nitride-based semiconductor layer and surrounds the gate protection layer. By applying the above configuration, the gate protection layer can release the thermal stress generated by the passivation layer. The gate protection layer can protect the gate electrode from be