US-12628370-B2 - Semiconductor device with multilayer source and drain regions formed in openings of electron supply and transit layers

Abstract

A semiconductor device according to one aspect of the present disclosure includes a substrate including a first main surface, a semiconductor layer provided on the first main surface of the substrate, and a gate electrode, a source electrode, and a drain electrode, provided on the semiconductor layer. The semiconductor layer has an electron transit layer provided above the substrate and including a first upper surface, and an electron supply layer provided above the electron transit layer. The electron supply layer and the electron transit layer have a first opening and a second opening. A bottom surface of the first opening and a bottom surface of the second opening each exist at a deeper position toward the substrate than the first upper surface.

Inventors

• Daiki TAKAYAMA

Assignees

• SUMITOMO ELECTRIC INDUSTRIES, LTD.

Dates

Publication Date

20260512

Application Date

20220531

Priority Date

20210607

Claims (9)

1. 1 . A semiconductor device comprising: a substrate including a first main surface; a semiconductor layer provided on the first main surface of the substrate; and a gate electrode, a source electrode, and a drain electrode, provided on the semiconductor layer, wherein the semiconductor layer has an electron transit layer provided above the substrate and including a first upper surface, and an electron supply layer provided above the electron transit layer, wherein the electron supply layer and the electron transit layer have a first opening and a second opening, and a bottom surface of the first opening and a bottom surface of the second opening each exist at a deeper position toward the substrate than the first upper surface, wherein the semiconductor layer further has a first source region containing a first electrically conductive impurity, provided on the bottom surface of the first opening, and including a second upper surface, a second source region containing the first electrically conductive impurity and provided on the second upper surface of the first source region, a first drain region containing the first electrically conductive impurity, provided on the bottom surface of the second opening, and including a third upper surface, and a second drain region containing the first electrically conductive impurity and provided on the third upper surface of the first drain region, wherein the source electrode is provided on the second source region, wherein the drain electrode is provided on the second drain region, wherein a concentration of the first electrically conductive impurity in the second source region is lower than a concentration of the first electrically conductive impurity in the first source region, wherein a concentration of the first electrically conductive impurity in the second drain region is lower than a concentration of the first electrically conductive impurity in the first drain region, wherein at least one of the first source region, the second source region, the first drain region, and the second drain region contains a rare gas element selected from the group consisting of Ar, Kr, or Xe, and wherein a nitride compound of the first electrically conductive impurity is present on each of the second upper surface of the first source region and the third upper surface of the first drain region.
2. 2 . The semiconductor device according to claim 1 , wherein the electron supply layer contains the first electrically conductive impurity at a concentration lower than the concentrations of the first electrically conductive impurities in the first source region, the second source region, the first drain region, and the second drain region.
3. 3 . The semiconductor device according to claim 1 , wherein the second source region is thinner than the first source region, and wherein the second drain region is thinner than the first drain region.
4. 4 . The semiconductor device according to claim 1 , wherein the first source region and the first drain region each contain the first electrically conductive impurity at a concentration equal to 90% or higher of a solid solubility limit at 25° C.
5. 5 . The semiconductor device according to claim 1 , wherein, within 90% of the first source region toward a lower side thereof in a thickness direction, a maximum value of the concentration of the first electrically conductive impurity is less than or equal to 1.1 times a minimum value of the concentration of the first electrically conductive impurity, and wherein, within 90% of the first drain region toward a lower side thereof in a thickness direction, a maximum value of the concentration of the first electrically conductive impurity is less than or equal to 1.1 times a minimum value of the concentration of the first electrically conductive impurity.
6. 6 . The semiconductor device according to claim 1 , wherein, within 90% of the second source region toward an upper side thereof in a thickness direction, a maximum value of the concentration of the first electrically conductive impurity is less than or equal to 1.1 times a minimum value of the concentration of the first electrically conductive impurity, and wherein, within 90% of the second drain region toward an upper side thereof in a thickness direction, a maximum value of the concentration of the first electrically conductive impurity is less than or equal to 1.1 times a minimum value of the concentration of the first electrically conductive impurity.
7. 7 . The semiconductor device according to claim 1 , wherein the concentration of the first electrically conductive impurity in each of the first source region, the second source region, the first drain region, and the second drain region is 1×10 19 cm −3 or higher.
8. 8 . The semiconductor device according to claim 1 , wherein the concentration of the first electrically conductive impurity in the second source region is less than or equal to 0.8 times the concentration of the first electrically conductive impurity in the first source region, and wherein the concentration of the first electrically conductive impurity in the second drain region is less than or equal to 0.8 times the concentration of the first electrically conductive impurity in the first drain region.
9. 9 . A semiconductor device comprising: a substrate including a first main surface; a semiconductor layer provided on the first main surface of the substrate; and a gate electrode, a source electrode, and a drain electrode, provided on the semiconductor layer, wherein the semiconductor layer has an electron transit layer provided above the substrate and including a first upper surface, and an electron supply layer provided above the electron transit layer, wherein the electron supply layer and the electron transit layer have a first opening and a second opening, and a bottom surface of the first opening and a bottom surface of the second opening each exist at a deeper position toward the substrate than the first upper surface, wherein the semiconductor layer further has a first source region containing a first electrically conductive impurity, provided in the first opening, and including a second upper surface, a second source region containing the first electrically conductive impurity and provided on the second upper surface of the first source region, a first drain region containing the first electrically conductive impurity, provided in the second opening, and including a third upper surface, and a second drain region containing the first electrically conductive impurity and provided on the third upper surface of the first drain region, wherein the source electrode is provided on the second source region, wherein the drain electrode is provided on the second drain region, wherein the electron supply layer contains the first electrically conductive impurity at a concentration lower than the concentrations of the first electrically conductive impurities in the first source region, the second source region, the first drain region, and the second drain region, wherein a concentration of the first electrically conductive impurity in the second source region is lower than a concentration of the first electrically conductive impurity in the first source region, wherein a concentration of the first electrically conductive impurity in the second drain region is lower than a concentration of the first electrically conductive impurity in the first drain region, wherein the second source region is thinner than the first source region, wherein the second drain region is thinner than the first drain region, wherein the first source region and the first drain region each contain the first electrically conductive impurity at a concentration equal to 90% or higher of a solid solubility limit at 25° C., wherein at least one of the first source region, the second source region, the first drain region, and the second drain region contains a rare gas element selected from the group consisting of Ar, Kr, and Xe, and wherein a nitride compound of the first electrically conductive impurity is present on each of the second upper surface of the first source region and the third upper surface of the first drain region.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority to Japanese Patent Application No. 2021-095288 filed on Jun. 7, 2021, and the entire contents of the Japanese patent application are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. BACKGROUND ART For high electron mobility transistors (HEMT), methods have been proposed to reduce the contact resistance, which represents the total resistance components between the source and drain electrodes and the two dimensional electron-gas (2DEG). In this method, openings are formed in an electron supply layer and an electron transit layer, a GaN (n+GaN) layer containing an n-type impurity at a high concentration is regrown in the openings by a metal organic chemical vapor deposition (MOCVD) method, and a source electrode and a drain electrode are formed on the n+GaN layer. [Patent Document 1] U.S. Pat. No. 9,515,161[Patent Document 2] U.S. Patent Application Publication No. US2008/0176366 SUMMARY OF THE INVENTION A semiconductor device according to the present disclosure includes a substrate including a first main surface, a semiconductor layer provided on the first main surface of the substrate, and a gate electrode, a source electrode, and a drain electrode, provided on the semiconductor layer. The semiconductor layer has an electron transit layer provided above the substrate and including a first upper surface, and an electron supply layer provided above the electron transit layer. The electron supply layer and the electron transit layer have a first opening and a second opening. A bottom surface of the first opening and a bottom surface of the second opening each exist at a deeper position toward the substrate than the first upper surface. The semiconductor layer further has a first source region containing a first electrically conductive impurity, provided on the bottom surface of the first opening, and including a second upper surface, a second source region containing the first electrically conductive impurity and provided on the second upper surface of the first source region, a first drain region containing the first electrically conductive impurity, provided on the bottom surface of the second opening, and including a third upper surface, and a second drain region containing the first electrically conductive impurity and provided on the third upper surface of the first drain region. The source electrode is provided on the second source region. The drain electrode is provided on the second drain region. A concentration of the first electrically conductive impurity in the second source region is lower than a concentration of the first electrically conductive impurity in the first source region. A concentration of the first electrically conductive impurity in the second drain region is lower than a concentration of the first electrically conductive impurity in the first drain region. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. FIG. 2 is a view illustrating an example of a concentration profile of n-type impurities during regrowth. FIG. 3 is a cross-sectional view (part 1) illustrating the method of manufacturing the semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view (part 2) illustrating the method of manufacturing the semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view (part 3) illustrating the method of manufacturing the semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view (part 4) illustrating the method of manufacturing the semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view (part 5) illustrating the method of manufacturing the semiconductor device according to the embodiment. FIG. 8 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 9 is a cross-sectional view (part 7) illustrating the method of manufacturing the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION When an n+GaN layer is formed by a conventional method, a decrease in throughput (the number of processed wafers per unit time when film formation is continuously performed on a plurality of wafers) is significant. An object of the present disclosure is to provide a semiconductor device capable of reducing contact resistance while suppressing a decrease in throughput, and a method of manufacturing the semiconductor device. Description of Embodiments of the Present Disclosure Embodiments of the present disclosure are first listed and described. A semiconductor device according to one aspect of the present disclosure includes a substrate including a first main surface, a semiconductor layer provided on the first main surface of the substrat