US-12628372-B2 - Capacitance reduction for backside power rail device

Abstract

The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Inventors

• Li-Zhen YU
• Lin-Yu HUANG
• Cheng-Chi Chuang
• Chih-Hao Wang
• Huan-Chieh Su

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20240104

Claims (20)

1. 1 . A semiconductor device, comprising: an epitaxial structure; a dielectric structure on a first side of the epitaxial structure; an air gap between the epitaxial structure and the dielectric structure, wherein the air gap is in contact with the dielectric structure; and a contact structure in contact with a second side of the epitaxial structure, wherein the second side is opposite to the first side.
2. 2 . The semiconductor device of claim 1 , wherein the air gap is in contact with the first side of the epitaxial structure.
3. 3 . The semiconductor device of claim 1 , further comprising a silicide layer on the first side of the epitaxial structure, wherein the silicide layer is between the air gap and the epitaxial structure.
4. 4 . The semiconductor device of claim 3 , further comprising a layer of dielectric material in contact with the silicide layer, wherein the air gap is between the layer of dielectric material and the dielectric structure.
5. 5 . The semiconductor device of claim 1 , further comprising a seal structure on the first side of the epitaxial structure, wherein the seal structure, the dielectric structure, and the epitaxial structure enclose the air gap.
6. 6 . The semiconductor device of claim 1 , further comprising an interconnect structure on the second side of the epitaxial structure and in contact with the contact structure.
7. 7 . The semiconductor device of claim 1 , wherein the contact structure comprises a silicide layer.
8. 8 . A semiconductor device, comprising: first and second source/drain (S/D) regions in contact with opposite ends of a channel structure; a first contact structure in contact with the first S/D region; a capping structure above the second S/D region; an air gap between the capping structure and the second S/D region; a dielectric structure above the air gap and extending through the capping structure, wherein the air gap is in contact with bottom surfaces of the dielectric structure and the capping structure; and a second contact structure in contact with the second S/D region and on a side of the second S/D region vertically opposite to the air gap.
9. 9 . The semiconductor device of claim 8 , further comprising a silicide layer on the second S/D region and in contact with the air gap.
10. 10 . The semiconductor device of claim 8 , wherein the dielectric structure, the capping structure, and the second S/D region enclose the air gap.
11. 11 . The semiconductor device of claim 8 , further comprising a seal dielectric layer, wherein the seal dielectric layer is on the second S/D region.
12. 12 . The semiconductor device of claim 8 , wherein the air gap is in contact with the second S/D region.
13. 13 . The semiconductor device of claim 8 , wherein the second contact structure comprises a silicide layer in contact with the second S/D region.
14. 14 . The semiconductor device of claim 8 , further comprising: a first interconnect structure in contact with the first contact structure; and a second interconnect structure in contact with the second contact structure.
15. 15 . A method, comprising: forming a source/drain (S/D) region on a substrate; forming a contact structure on the S/D region; forming a dielectric structure on the contact structure; and removing at least a portion of the contact structure through the dielectric structure to form an air gap between the dielectric structure and the S/D region.
16. 16 . The method of claim 15 , wherein the removing at least the portion of the contact structure comprises: forming an opening in the dielectric structure; removing the contact structure through the opening to form the air gap; and forming a seal structure in the opening to seal the air gap.
17. 17 . The method of claim 16 , wherein the forming the seal structure comprises depositing a dielectric material on the dielectric structure to seal the opening.
18. 18 . The method of claim 15 , wherein the contact structure comprises a metal contact and a silicide layer, and wherein the removing at least the portion of the contact structure comprises: forming an opening in the dielectric structure; removing the metal contact through the opening to form the air gap; and forming a seal structure in the opening to seal the air gap, wherein the air gap is in contact with the silicide layer.
19. 19 . The method of claim 15 , further comprising: removing a portion of the S/D region on a side of the S/D region opposite to the air gap; and forming an additional contact structure in contact with the side of the S/D region opposite to the air gap.
20. 20 . The method of claim 19 , further comprising forming an interconnect structure in contact with the additional contact structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. Non-Provisional patent application Ser. No. 17/814,098, filed on Jul. 21, 2022, titled “Capacitance Reduction for Backside Power Rail Device,” which is a continuation of U.S. Non-Provisional patent application Ser. No. 17/069,344, filed on Oct. 13, 2020, titled “Capacitance Reduction for Backside Power Rail Device,” now U.S. Pat. No. 11,404,548, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). Such scaling down has increased the complexity of semiconductor manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. FIGS. 1A, 1B, and 1C illustrate an isometric view and various cross-sectional views of a backside power rail (BPR) semiconductor device with capacitance reduction using an air gap, in accordance with some embodiments. FIGS. 2A, 2B, 2C, and 2D illustrate cross-sectional views of various BPR semiconductor devices with capacitance reduction using an air gap, in accordance with some embodiments. FIG. 3 is a flow diagram of a method for fabricating a BPR semiconductor device with capacitance reduction using an air gap, in accordance with some embodiments. FIGS. 4-13 illustrate cross-sectional views of a BPR semiconductor device with capacitance reduction using an air gap at various stages of its fabrication process, in accordance with some embodiments. Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within