US-12628375-B2 - Nanosheet transistor with asymmetric junction and robust structure stability

Abstract

A semiconductor structure includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes a second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers.

Inventors

• Ruilong Xie
• Julien Frougier
• Kangguo Cheng
• Chanro Park

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20210929

Claims (19)

1. 1 . A semiconductor structure comprising: a substrate; bottom dielectric isolation (BDI) on the substrate; a nanosheet stack on the BDI, the nanosheet stack comprising: gate stack layers; and semiconductor nanosheets interleaved with the gate stack layers; a first source/drain region on the BDI, adjacent to and contacting the nanosheet stack; a second source/drain region extending from the top of the nanosheet stack down through the BDI to the substrate, adjacent to and contacting the nanosheet stack; and dielectric spacers on opposite sides of the gate stack layers, wherein the dielectric spacers have asymmetry in terms of at least their thickness between the opposite sides of the gate stack layers whereby the dielectric spacers share common sidewalls with ends of the semiconductor nanosheets while the dielectric spacers on one side of the gate stack layers are thicker than the dielectric spacers on another, opposite side of the gate stack layers, and wherein each of the dielectric spacers comprises a single layer of a spacer material.
2. 2 . The semiconductor structure of claim 1 , wherein the dielectric spacers comprise: first dielectric spacers that are adjacent to the first source/drain region and separate the first source/drain region from the gate stack layers.
3. 3 . The semiconductor structure of claim 2 , wherein the dielectric spacers further comprise: second dielectric spacers that are adjacent to the second source/drain region and separate the second source/drain region from the gate stack layers.
4. 4 . The semiconductor structure of claim 3 , wherein the first and second dielectric spacers comprise high-k dielectric material.
5. 5 . The semiconductor structure of claim 1 , wherein the gate stack layers comprise high-k dielectric material.
6. 6 . The semiconductor structure of claim 1 , wherein the semiconductor structure forms a field effect transistor (FET) with a gate atop the gate stack layers.
7. 7 . The semiconductor structure of claim 1 , wherein the first source/drain region is adjacent to and contacts both the nanosheet stack and an adjacent nanosheet stack.
8. 8 . The semiconductor structure of claim 7 , wherein one side of the first source/drain region is adjacent to and contacts the nanosheet stack, and wherein another opposite side of the first source/drain region is adjacent to and contacts the adjacent nanosheet stack.
9. 9 . The semiconductor structure of claim 7 , wherein the dielectric spacers that are thicker are on a different side of the nanosheet stack as compared to the adjacent nanosheet stack.
10. 10 . The semiconductor structure of claim 1 , further comprising: a first source/drain region metal contact that contacts the first source/drain region, wherein the first source/drain region metal contact is present entirely above the dielectric spacers; and a second source/drain region metal contact that contacts the second source/drain region, wherein the second source/drain region metal contact is present entirely above the dielectric spacers.
11. 11 . A semiconductor structure comprising: a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; a nanosheet stack on the BDI, the nanosheet stack comprising: gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers; a second source/drain region contacting the semiconductor nanosheets and extending from the top of the nanosheet stack down through the BDI to the substrate; a drain metal contact that contacts the first source/drain region, wherein the drain metal contact is present entirely above the first inner spacers; and a source metal contact that contacts the second source/drain region, wherein the source metal contact is present entirely above second inner spacers, wherein the nanosheet stack further comprises the second inner spacers that are adjacent to the second source/drain region and separate the second source/drain region from the gate stack layers, and wherein the first inner spacers have asymmetry in terms of at least their thickness as compared to the second inner spacers whereby the first inner spacers and the second inner spacers share common sidewalls with ends of the semiconductor nanosheets while the first inner spacers are thicker than the second inner spacers.
12. 12 . The semiconductor structure of claim 11 , wherein the first inner spacers and the second inner spacers are high-k material.
13. 13 . The semiconductor structure of claim 11 , further comprising: a gate atop the nanosheet stack; a drain metal contact that contacts the first source/drain region; a source metal contact that contacts the second source/drain region; and first and second gate dielectric spacers that electrically separate the gate from the drain metal contact and the source metal contact, wherein the semiconductor structure forms a field effect transistor (FET).
14. 14 . The semiconductor structure of claim 13 , further comprising: a gate dielectric cap atop the gate, wherein a top of the gate dielectric cap is coplanar with tops of the first and second gate dielectric spacers.
15. 15 . The semiconductor structure of claim 11 , wherein the second inner spacers are of different dielectric constant k, compared to the first inner spacers.
16. 16 . The semiconductor structure of claim 11 , wherein the second inner spacers are of different width, compared to the first inner spacers.
17. 17 . The semiconductor structure of claim 11 , wherein the second inner spacers have a higher k-value, compared to the first inner spacers.
18. 18 . The semiconductor structure of claim 11 , wherein the first source/drain region is adjacent to and contacts both the nanosheet stack and an adjacent nanosheet stack.
19. 19 . The semiconductor structure of claim 11 , wherein each of the first inner spacers and each of the second inner spacers comprises a single layer of a spacer material.

Description

BACKGROUND The present invention relates to the electrical, electronic, and computer arts, and more specifically, to nanosheet stack semiconductor structures. As semiconductor technology scales to smaller dimension nodes (e.g., 23 nm process to 7 nm process), increasing cell density requires increased cell height. During fabrication, taller, narrower new stacks are less mechanically stable than shorter, wider old stacks. Mechanical stability during fabrication enhances quality of fabrication results. Smaller dimension/denser semiconductor cells have increased leakage currents due to the smaller distance, and therefore smaller resistance, through the substrate between the source and the drain. Bottom dielectric isolation (BDI) sometimes is interposed between the source and drain and the semiconductor substrate in order to isolate the source and drain from the substrate. However, BDI interposition has the result that the semiconductor no longer can be grown epitaxially from the substrate. S/D Epitaxial growth from substrate enhances crystal structure (fewer defects) and potentially can introduce stress to the channel and thereby enhances electrical performance. SUMMARY Principles of the invention provide techniques for an asymmetric nanosheet transistor junction with robust structure stability. In one aspect, an exemplary semiconductor structure, according to an aspect of the invention, includes a substrate; bottom dielectric isolation (BDI) on the substrate; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers and semiconductor nanosheets interleaved with the gate stack layers. The structure also includes a first source/drain region on the BDI, adjacent to and contacting the nanosheet stack; and a second source/drain region extending from the top of the nanosheet stack down through the BDI to the substrate, adjacent to and contacting the nanosheet stack. Another aspect provides an exemplary semiconductor structure, which includes a substrate; bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; and a nanosheet stack on the BDI. The nanosheet stack includes gate stack layers; semiconductor nanosheets interleaved with the gate stack layers and contacting the first source/drain region; and first inner spacers adjacent to the first source/drain region and separating the first source/drain region from the gate stack layers. The structure also includes second source/drain region contacting the semiconductor nanosheet and extending from the top of the nanosheet stack down through the BDI to the substrate. Accordingly, the nanosheet stack also includes second inner spacers in the nanosheet stack adjacent to the second source/drain region and separating the second source/drain region from the gate stack layers. Another aspect provides a method, which includes, at, obtaining a first precursor structure. The first precursor structure includes a substrate; a bottom dielectric isolation (BDI) on the substrate; a first source/drain region on the BDI; a nanosheet stack of fins and sacrificial silicon germanium (SiGe) layers, disposed next to the first source/drain region; a dummy gate disposed on top of the nanosheet stack; a hard mask disposed on top of the dummy gate; and first gate spacers disposed at either side of the hard mask and the dummy gate. The first gate spacers and the dummy gate entirely occupy a top of the nanosheet stack. The method also includes, at, depositing an interlayer dielectric onto the first precursor structure; at, etching the hard mask; and at, forming intermediate spacers on the dummy gates and then etching the dummy gates between the intermediate spacers to form a trench. In view of the foregoing, techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide one or more of: A nanosheet stacked transistor junction precursor that exhibits robust structural stability during fabrication. A nanosheet stacked transistor junction with asymmetry between source and drain substrate connection, which improves electrical performance. A nanosheet stacked transistor junction with asymmetry between source side spacers and drain side spacers, which improves electrical performance. Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a nanosheet transistor junction, according to an exemplary embodiment. FIG. 2 depicts a flowchart of a process for fabricating the transistor junction shown in FIG. 1, according to an exemplary embodiment. FIG. 3 depicts a first precursor structure according to the process of FIG. 2. FIG