US-12628376-B2 - Nanosheet structures with tunable channels and inner sidewall spacers

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

Inventors

• Hong Yu
• David C. Pritchard
• Navneet K. Jain
• James P. Mazza
• Romain H. A. Feuillette

Assignees

• GLOBALFOUNDRIES U.S. INC.

Dates

Publication Date

20260512

Application Date

20230518

Claims (20)

1. 1 . A structure comprising: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of stacked semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures, wherein a thickness of the inner sidewall spacers has an inverse relationship to lengths of the gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.
2. 2 . The structure of claim 1 , wherein the length of the lower gate structure is less than the length of an uppermost gate structure of the plurality of gate structures.
3. 3 . The structure of claim 1 , wherein the inner sidewall spacers surround each of the plurality of gate structures along the length.
4. 4 . The structure of claim 1 , wherein the length of the lower gate structure is less than the length of any of the remaining gate structures of the plurality of gate structures.
5. 5 . The structure of claim 1 , wherein a middle gate structure of the plurality of gate structures has a largest length, and wherein the gate structures comprise a bow shape profile which results in an inverse bow shape structure of the inner sidewall spacers.
6. 6 . The structure of claim 1 , wherein the plurality of gate structures comprise wraparound gate structures.
7. 7 . The structure of claim 1 , wherein the inner sidewall spacer for each of the plurality of gate structures has a different thickness.
8. 8 . The structure of claim 1 , wherein the inner sidewall spacer for each of the plurality of gate structures has a same thickness.
9. 9 . The structure of claim 1 , wherein the inner sidewall spacer for the lower gate structure has a thickness greater than the inner sidewall spacer for the each remaining gate structure of the plurality of gate structures.
10. 10 . The structure of claim 1 , further comprising a top gate structure over an uppermost nanosheet of the plurality of stacked semiconductor nanosheets.
11. 11 . The structure of claim 1 , wherein the plurality of stacked semiconductor nanosheets comprise Si material.
12. 12 . The structure of claim 1 , wherein the source/drain regions comprise raised source/drain regions adjacent to each of the plurality of gate structures and a lowest gate structure of the plurality of gate structures is over the semiconductor substrate.
13. 13 . The structure of claim 1 , wherein the plurality of gate structures comprise wraparound structures and the thickness of the inner sidewall spacers includes an inverse relationship to a channel length of the wraparound structures, with the lower gate structure having a shortest channel length and a thickest inner sidewall spacer and an uppermost gate structure having a larger channel length and a thinnest inner sidewall spacer.
14. 14 . The structure of claim 1 , further comprising a sidewall spacer surrounding the top gate structure and the inner sidewall spacers.
15. 15 . A structure comprising: a plurality of stacked semiconductor nanosheets; a plurality of gate structures surrounding individual nanosheets of the plurality of stacked semiconductor nanosheets, the plurality of gate structures comprising an inverse tapered profile, and wherein the plurality of gate structures are vertically stacked wraparound gate structures; inner sidewall spacers adjacent each of the plurality of gate structures, wherein a thickness of the inner sidewall spacers has an inverse relationship to lengths of the gate structures; and source/drain regions on opposing sides of the plurality of gate structures.
16. 16 . The structure of claim 15 , wherein a lower gate structure of the plurality of gate structures comprises a gate length smaller than any upper gate structure of the plurality of gate structures.
17. 17 . The structure of claim 16 , wherein a lower inner sidewall spacer associated with the lower gate structure comprises a thickness greater than any upper inner sidewall spacer of the inner sidewall spacers.
18. 18 . The structure of claim 15 , wherein the inner sidewall spacers separate the source/drain regions from the plurality of gate structures.
19. 19 . The structure of claim 15 , wherein the stacked semiconductor nanosheets comprise Si material.
20. 20 . A method comprising: forming a plurality of stacked semiconductor nanosheets over a semiconductor substrate; forming a plurality of gate structures surrounding individual nanosheets of the plurality of stacked semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures, and wherein the plurality of gate structures are vertically stacked wraparound gate structures; forming an inner sidewall spacer adjacent each of the plurality of gate structures, wherein the thickness of the inner sidewall spacers has an inverse relationship to the length of the gate structures; and forming source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

Description

BACKGROUND The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. Gate-All-Around (GAA) nanosheet field effect transistors (FETs) include stacks of nanosheets or nanowires with spacers that are surrounding the full perimeter of multiple nanosheet channel regions with a metal gate stack. Nanosheet transistors have increased performance over planar transistors by providing increased device density and performance. Nanosheet FETs are prone to a tapered profiling resulting in narrower (e.g., shorter) nanosheets with thicker inner sidewall spacers at the topmost nanosheet (the nanosheet closest to the top metal gate) and wider (e.g., longer) nanosheets with thinner inner sidewall spacers at the bottom nanosheet (the nanosheet closest to the channel of the substrate). Nanosheet FETs exhibit losses in performance at the bottom of the device, e.g., nanosheets nearest the substrate. Thus, the wider nanosheets (nearest the channel) provide lower performance through drivability to the FET. Further, as GAA nanosheet FETs become larger (with more layers), the tapered profiling becomes further exaggerated, with losses in performance becoming greater. SUMMARY In an aspect of the disclosure, a structure comprises: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer. In an aspect of the disclosure, a structure comprises: a plurality of stacked semiconductor nanosheets; a plurality of gate structures surrounding individual nanosheets of the stacked semiconductor nanosheets, the plurality of gate structures comprising an inverse tapered profile; inner sidewall spacers adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures. In an aspect of the disclosure, a method comprises: forming a plurality of stacked semiconductor nanosheets over a semiconductor substrate; forming a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; forming an inner sidewall spacer adjacent each of the plurality of gate structures; and forming source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. FIG. 1 shows a cross-sectional view of a nanosheet field effect transistor (FET) in accordance with aspects of the present disclosure. FIG. 2 shows a cross-sectional view of a nanosheet FET in accordance with additional aspects of the present disclosure. FIG. 3 shows a cross-sectional view of a nanosheet FET in accordance with further aspects of the present disclosure. FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, and 4I show cross-sectional views of respective fabrication processes of a nanosheet FET in accordance with aspects of the present disclosure. DETAILED DESCRIPTION The present disclosure relates to semiconductor structures and, more particularly, to nanosheet field effect transistors (FET). More specifically, the present disclosure comprises gate structures (FETs) wrapped around nanosheets and comprising tunable channels and inner sidewall spacers. For example, in embodiments, the lower gate structure may have the smallest channel length, with the thickest inner sidewall spacer. Alternatively, all of the gate structures, e.g., wraparound gate structures and respective inner sidewall spacers may have uniform gate lengths and thicknesses, respectively. Advantageously, the structures and processes described herein reduce losses in performance, for example, from carrying less current but with the same capacitance. In more specific embodiments, the processes described provide independently tunable gate structures (e.g., channel lengths) and inner sidewall spacers for the wraparound gate structures. For example, in embodiments, the thicknesses of the inner sidewall spacers and channel length of the gate structures wrapping around the nanosheets can be adjusted at different levels of the structure. For example, the gate length of the gate structures can be tuned to ha