US-12628377-B2 - Gate-all-around (GAA) field-effect transistor (FET) device having FETs with different crystalline orientation channels through a substrate

Abstract

A gate-all-around (GAA) field effect transistor (FET) device, and related fabrication methods are disclosed. The GAA FET device includes P-type semiconductor PFET(s) and N-type semiconductor NFET(s) having channels with different crystalline orientation through a substrate. The GAA PFET(s) includes a channel structure of a first type of crystalline orientation (e.g., <110> or <111>) and the GAA NFET(s) include a channel structure of a second type of crystalline orientation (e.g., <100>) different from the first type of crystalline orientation of the GAA PFET(s). The different crystalline orientation channels improve the balance of carrier mobility for both carrier types (i.e., P-type and N-type) of GAA FETs in the GAA FET device. In one aspect, the different crystalline orientation channels are provided through a substrate to increase and/or balance carrier mobility between GAA PFET(s) and NFET(s) to achieve a more balanced drive strength between these types of transistors.

Inventors

• Shreesh Narasimha
• Yan Sun
• Peijie Feng

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260512

Application Date

20230622

Claims (17)

1. 1 . A gate-all-around (GAA) field-effect transistor (FET) device, comprising: a substrate, comprising: a first region having a first crystalline orientation; an isolation layer in the substrate; a second region on the isolation layer having a second crystalline orientation; a spacer in the substrate, wherein the spacer extends to a same depth into the substrate as the isolation layer; and an isolation structure in the substrate; a GAA P-type semiconductor FET (PFET) having a P-type channel in the first region, wherein the P-type channel has the first crystalline orientation; and a GAAN-type semiconductor FET (NFET) having an N-type channel in the second region, wherein the N-type channel has the second crystalline orientation.
2. 2 . The GAA FET device of claim 1 , wherein: the P-type channel comprises a first P-type channel structure and a second P-type channel structure; the N-type channel comprises a first N-type channel structure and a second N-type channel structure; the first P-type channel structure is co-planar with the first N-type channel structure; and the second P-type channel structure is co-planar with the second N-type channel structure.
3. 3 . The GAA FET device of claim 1 , wherein the P-type channel has the first crystalline orientation that comprises a <110> crystalline orientation.
4. 4 . The GAA FET device of claim 1 , wherein the N-type channel has the second crystalline orientation that comprises a <100> crystalline orientation.
5. 5 . The GAA FET device of claim 1 , wherein the spacer separates the isolation layer and the isolation structure.
6. 6 . The GAA FET device of claim 1 , wherein the isolation layer comprises silicon dioxide (SiO 2 ).
7. 7 . The GAA FET device of claim 1 , wherein the isolation structure separates the spacer and the first region of the substrate.
8. 8 . The GAA FET device of claim 1 , wherein the isolation structure extends deeper into the substrate than the spacer.
9. 9 . The GAA FET device of claim 1 integrated into an integrated circuit (IC).
10. 10 . The GAA FET device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; a drone; and a multicopter.
11. 11 . A method of fabricating a gate-all-around (GAA) field effect transistor (FET) device, comprising: providing a substrate comprising a first region having a first crystalline orientation, an isolation layer in the substrate, and a second region on the isolation layer having a second crystalline orientation; forming a spacer in the substrate to extend to a same depth into the substrate as the isolation layer; forming an isolation structure in the substrate; forming a GAA P-type semiconductor FET (PFET) having a P-type channel in the first region, wherein the P-type channel has the first crystalline orientation; and forming a GAA N-type semiconductor FET (NFET) having an N-type channel in the second region, wherein the N-type channel has the second crystalline orientation.
12. 12 . The method of claim 11 , wherein: forming the GAA PFET having the P-type channel comprises forming a first P-type channel structure and a second P-type channel structure; forming the GAA NFET having the N-type channel comprises forming a first N-type channel structure in a same fabrication step as the first P-type channel structure and a second N-type channel structure in a same fabrication step as the second P-type channel structure; the first P-type channel structure is co-planar with the first N-type channel structure; and the second P-type channel structure is co-planar with the second N-type channel structure.
13. 13 . The method of claim 12 , wherein the P-type channel comprises a <110> crystalline orientation.
14. 14 . The method of claim 11 , wherein the N-type channel comprises a <100> crystalline orientation.
15. 15 . The method of claim 11 , wherein forming the spacer further comprises forming the spacer to separate the isolation layer and the isolation structure.
16. 16 . The method of claim 11 , wherein forming the isolation structure further comprises forming the isolation structure to separate the spacer and the first region of the substrate.
17. 17 . The method of claim 11 , wherein forming the isolation structure comprises forming the isolation structure to extend deeper into the substrate than the spacer.

Description

BACKGROUND I. Field of the Disclosure The technology of the disclosure relates generally to field-effect transistors (FETs), and more particularly to gate-all-around (GAA) FETs. II. Background Transistors are essential components in modern electronic devices. Large numbers of transistors are employed in integrated circuits (ICs) in many modern electronic devices. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices. As electronic devices become more complex in functionality, so does the need to increase the number of transistors in such devices, while sustaining or increasing the performance of these devices. Planar field-effect transistors (FETs) are made up of a channel of semiconductor material, typically silicon, which is sandwiched between two electrodes, the source, and the drain. The flow of current through the channel is controlled by an electric field, which is applied by a gate electrode that is placed on top of the channel and separated from it by a thin insulating layer. Planar transistors are characterized by their flat, planar geometry, which provides a simple and compact design that is easy to manufacture and integrate into complex circuits. An increase in the number of transistors is achieved in part through continued efforts to miniaturize transistors in ICs (i.e., placing increasingly more transistors into the same amount of space). To provide greater numbers of transistors, their gate lengths are reduced in a scalable fashion, thereby reducing channel length of the transistors. For example, as the channel length in planar transistors is reduced such that the channel length is of the same order of magnitude as depletion layer widths, short channel effects (SCEs) can occur that degrade performance. More specifically, SCEs in planar transistors cause increased current leakage, reduced threshold voltage, and/or threshold voltage roll-off (i.e., reduced threshold voltage at shorter gate lengths), and therefore, reduced gate control. In this regard, alternative FET designs to planar FETs have been developed. These alternative transistor designs provide for a gate material to wrap around at least a portion of a channel structure to provide better gate control over an active channel therein. Better gate control provides reduced current leakage and increased threshold voltage compared to a planar FET of a similar footprint. One example of a gate around FET is a FinFET. A FinFET provides a channel structure formed by a thin semiconductor material “fin” disposed above the substrate between a source and the drain. The FinFET also includes a “wrap-around” gate that wraps around top and side portions of the fin to provide gate control of the channel formed by the channel structure. However, it has become difficult to scale down the size of FinFETs due to fabrication and performance limitations. In this regard, gate-all-around (GAA) FETs have been further developed. A GAA FET includes one or more nano channel structures of semiconductor material (e.g., nanowires or nanosheets) that are stacked in relationship to each other and disposed between a source and a drain. Each nano channel structure forms part of the channel of the GAA FET. To provide better gate control of the channel, gate material is disposed all around each of the channel structures as well as between adjacent channel structures. This provides an even greater gate in the GAA FET to provide reduced current leakage and increased threshold voltage in compared to a planar FET and/or FinFET. SUMMARY Aspects disclosed in the detailed description include a gate-all-around (GAA) field-effect transistor (FET) device having FETs with different crystalline orientation channels through a substrate having first and second regions. Related fabrications methods are also disclosed. For example, the FETs in the GAA FET device can include both a GAA P-type semiconductor material FET(s) (PFET(s)) and a GAA N-type semiconductor material FET(s) (NFET(s)) which can be included as part of a complementary metal oxide semiconductor (CMOS) circuit. The GAA PFET(s) and the GAA NFET(s) in the GAA FET device each include a semiconductor channel (“channel”) that includes one or more semiconductor channel structures (“channel structures”) (e.g., a nanosheet, a nanowire). A source and drain are disposed on opposite sides of the channels. In an exemplary aspect, the GAA PFET(s) in the GAA FET device includes a P-type channel structure of a first crystalline orientation (e.g., <110> or <111>), and the GAA NFET(s) in the GAA FET device includes a N-type channel structure of a second crystalline orientation (e.g., <100>) that is different from the first crystalline orientation of the GAA PFET(s). The GAA FET device with different crystalline orientation channels improves the balance of carrier mobility for both carrier types (i.e., P-type and N-type) of GAA FETs in