US-12628378-B2 - Semiconductor manufacturing

US12628378B2US 12628378 B2US12628378 B2US 12628378B2US-12628378-B2

Abstract

Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source/drain depths, and/or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

Inventors

Jhon Jhy Liaw

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230622

Claims (20)

1 . A semiconductor device, comprising: a semiconductor substrate; a first gate stack and a second gate stack disposed over the semiconductor substrate, wherein at least one of the first gate stack and the second gate stack comprises a plurality of gate layers, and wherein the first gate stack and the second gate stack have an air gap there between; a first nanostructure extending through the first gate stack and a second nanostructure extending through the second gate stack; a first gate structure and a second gate structure disposed over the first gate stack and the second gate stack, respectively; a first dielectric landing pad disposed over a top surface and upper sidewalls of the first gate structure, wherein the first dielectric landing pad is planar with a source/drain contact; a first plug disposed over the first dielectric landing pad and electrically connected to the first gate structure, wherein a width of the first gate structure is greater than a width of the first plug; a dielectric layer disposed over the first gate stack, wherein the first dielectric landing pad and the first plug are surrounding by the dielectric layer; and source/drain regions on opposing sides of the first nanostructure and the second nanostructure, the source/drain regions overlapping an isolation margin region of the semiconductor substrate, the isolation margin region including anti-punch through dopants.
2 . The semiconductor device of claim 1 , further comprising: a second dielectric landing pad disposed over a top surface and upper sidewalls of the second gate structure; and a second plug disposed over the second dielectric landing pad and electrically connected to the second gate structure, wherein a distance between the first plug and the second plug is greater than a distance between the first gate stack and the second gate stack.
3 . The semiconductor device of claim 1 , wherein the first dielectric landing pad is in direct contact with the dielectric layer.
4 . The semiconductor device of claim 1 , wherein the first nanostructure is spaced apart from the semiconductor substrate by a first spacing, and the second nanostructure is spaced apart from the first nanostructure by a second spacing, the second spacing being less than the first spacing.
5 . The semiconductor device of claim 4 , wherein a concentration gradient of the anti-punch through dopants does not extend into the first nanostructure.
6 . The semiconductor device of claim 5 , wherein the first spacing is between about 6 nm and about 20 nm.
7 . The semiconductor device of claim 6 , wherein the second spacing is between about 5 nm and about 12 nm.
8 . A semiconductor device, comprising: a first gate stack and a second gate stack over a semiconductor substrate, wherein at least one of the first gate stack and the second gate stack comprises a plurality of gate layers, and wherein the first gate stack and the second gate stack have an air gap therebetween; a first nanostructure that extends through the first gate stack; a first gate structure and a second gate structure over the first gate stack and the second gate stack, respectively; a first dielectric layer surrounding the first gate structure and the second gate structure; a first dielectric landing pad over a top surface and upper sidewalls of the first gate structure and a second dielectric landing pad over a top surface and upper sidewalls of the second gate structure; a second dielectric layer overlying the first dielectric landing pad and the second dielectric landing pad; a first source/drain adjacent to the first gate stack; an isolation margin region of anti-punch through dopants between the first source/drain and the semiconductor substrate; a first source/drain contact in physical contact with the first source/drain, the first source/drain contact being planar with the first dielectric landing pad; and a first plug in the second dielectric layer and over the first dielectric landing pad, wherein a width of the first gate structure is greater than a width of the first plug.
9 . The semiconductor device of claim 8 , further comprising: a second plug in the second dielectric layer and over the second dielectric landing pad, wherein a distance between the first plug and the second plug is greater than a distance between the first gate stack and the second gate stack.
10 . The semiconductor device of claim 8 , further comprising dopants to obstruct punch through in the semiconductor substrate.
11 . The semiconductor device of claim 8 , wherein the first nanostructure is separated from the semiconductor substrate by a first spacing, and a second nanostructure extends through the first gate stack and is separated from the first nanostructure by a second spacing less than the first spacing.
12 . The semiconductor device of claim 11 , wherein a bottom of the first gate stack is closer to the semiconductor substrate than a bottom of the first source/drain.
13 . The semiconductor device of claim 11 , wherein the second spacing is between about 5 nm and about 12 nm.
14 . A semiconductor device, comprising: a first stack of nanostructures over a semiconductor substrate; a second stack of nanostructures over the semiconductor substrate; a first gate electrode, wherein a first portion of the first gate electrode is within the first stack of nanostructures and wherein a second portion of the first gate electrode is over the first stack of nanostructures; a second gate electrode, wherein a first portion of the second gate electrode is within the second stack of nanostructures and wherein a second portion of the second gate electrode is over the second stack of nanostructures; a first cap disposed over a top surface and upper sidewalls of the first gate electrode, the first cap having a planar top surface, the planar top surface aligned with a top surface of a source/drain contact; a first plug disposed over the first cap and electrically connected to the first gate electrode, wherein a width of the first gate electrode is greater than a width of the first plug; a dielectric layer on opposing sides of the first cap and the first plug; and source/drain regions on opposing sides of the first stack of nanostructures and the second stack of nanostructures, the source/drain regions separated from the semiconductor substrate by an isolation margin region of anti-punch through dopants.
15 . The semiconductor device of claim 14 , further comprising a second cap disposed over a top surface and upper sidewalls of the second gate electrode.
16 . The semiconductor device of claim 15 , further comprising a second plug disposed over the second cap and electrically connected to the second gate electrode, wherein a width of the second gate electrode is greater than a width of the second plug.
17 . The semiconductor device of claim 14 , further comprising: a first nanostructure within the first stack of nanostructures and separated from the semiconductor substrate by a first spacing; and a second nanostructure within the first stack of nanostructures and separated from the first nanostructure by a second spacing less than the first spacing.
18 . The semiconductor device of claim 17 , further comprising dopants to obstruct punch through in the semiconductor substrate.
19 . The semiconductor device of claim 18 , wherein a concentration gradient of the dopants to obstruct punch through does not extend into the first nanostructure.
20 . The semiconductor device of claim 17 , wherein the first spacing is between about 6 nm and about 20 nm, and the second spacing is between about 5 nm and about 12 nm.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 17/843,533, filed on Jun. 17, 2022, entitled “Semiconductor Manufacturing,” which is a division of U.S. patent application Ser. No. 16/780,059, filed on Feb. 3, 2020, entitled “Semiconductor Manufacturing,” now U.S. Pat. No. 11,367,782 issued on Jun. 21, 2022, which claims the benefit of U.S. Provisional Application No. 62/894,250, filed on Aug. 30, 2019, entitled “Semiconductor Devices and Methods of Manufacturing,” which applications are hereby incorporated herein by reference. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-11 illustrate intermediate steps in the formation of a semiconductor device, in accordance with some embodiments. FIG. 12A illustrates a physical layout of the semiconductor device comprising a set of GAA transistors, in accordance with some embodiments. FIG. 12B illustrates a cross-sectional view through a set of the GAA transistors in the semiconductor device of FIG. 12A, the set of GAA transistors being arranged as a CMOS device, in accordance with some embodiments. FIG. 13 illustrates cross-sectional views through a first GAA transistor formed as an NMOSFET and a second GAA transistor formed as a PMOSFET of the semiconductor device, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments will now be described with respect to the integration of horizontal gate-all-around nanostructure transistors for use in the design and operation of integrated circuits in the 5 nm technology node and below. Such embodiments help to mitigate bottom sheet threshold voltage (Vt) shift issues that are induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. Embodiments, however, may be utilized in a wide variety of ways, and are not intended to be limited to the embodiments described herein. With reference now to FIG. 1, there is illustrated a substrate 101 into which dopants have been implanted in order to form wells. In an embodiment the substrate 101 is a semiconductor substrate, which may be, for example, a silicon substrate, a silicon germanium substrate, a germanium s