US-12628379-B2 - Thin film transistor and display panel

US12628379B2US 12628379 B2US12628379 B2US 12628379B2US-12628379-B2

Abstract

A thin film transistor including a base substrate, and a drain, a source and an active layer on the base substrate, where the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other.

Inventors

Dongfang Wang
Lizhong Wang
Ce Ning

Assignees

BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20220331

Claims (7)

1 . A display panel, comprising a plurality of thin film transistors, each of which comprises a base substrate, and a drain, a source and an active layer on the base substrate, wherein the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other, wherein the display panel further comprises a plurality of gate lines extending along a first direction and arranged at intervals, and a plurality of data lines extending along a second direction and arranged at intervals, wherein the first direction and the second direction intersect with each other; wherein, a position, where an orthographic projection of each of the plurality of gate lines on the base substrate and an orthographic projection of each of the plurality of data line on the base substrate overlap each other, at least partially overlaps an orthographic projection of a corresponding one of the plurality of thin film transistors on the base substrate, wherein the display panel comprises a plurality of pixel structures, each of the plurality of pixel structures comprises three sub-pixel structures of different colors, and each of the three sub-pixel structures comprises a corresponding one of the plurality of thin film transistors, wherein the thin film transistor further comprises a gate, a connecting electrode, an interlayer insulating layer and a first insulating layer, the first insulating layer is on a side of the gate away from the base substrate, the interlayer insulating layer is between the source and the drain, and the connecting electrode is on a side of the first insulating layer away from the gate; the thin film transistor is provided with a second via penetrating through the interlayer insulating layer and the first insulating layer, and the connecting electrode is connected to the source through the second via; and for the three thin film transistors in a same pixel structure, the orthographic projection of the second via in one of the three thin film transistors on the base substrate at least partially overlaps the orthographic projection of one corresponding data line on the base substrate, and the orthographic projections of the second vias of different thin film transistors on the base substrate at least partially overlap the orthographic projections of different data lines on the base substrate, respectively.
2 . The display panel according to claim 1 , wherein the gate, the drain, the source and the active layer are arranged in different layers, respectively; an orthographic projection of the gate on the base substrate at least partially overlaps any one of the orthographic projection of the drain on the base substrate, the orthographic projection of the source on the base substrate and the orthographic projection of the active layer on the base substrate; wherein the drain is on a side of the source close to the base substrate, and the gate is on a side of the source away from the base substrate; wherein the thin film transistor further comprises an interlayer insulating layer between the source and the drain, wherein the thin film transistor is provided with a first via penetrating through the source and the interlayer insulating layer, and an orthographic projection of the first via on the base substrate is within the orthographic projection of the drain on the base substrate; wherein the active layer comprises a planar part and a recessed part connected to the planar part; the planar part is on a side of the source away from the drain, and is connected to the source; the recessed part is connected to a part of the planar part at the first via, and the recessed part is concave towards the drain along an inner wall of the first via and is connected to the drain; and the position, where an orthographic projection of each of the plurality of gate lines on the base substrate and an orthographic projection of each of the plurality of data line on the base substrate overlap each other, is referred to as an intersection, and the orthographic projection of the first via in the thin film transistor at the intersection on the base substrate at least partially overlaps the intersection.
3 . The display panel according to claim 2 , wherein the first vias of the thin film transistors on a same gate line are arranged side by side in the first direction.
4 . The display panel according to claim 2 , wherein the thin film transistors on a same gate line are divided into a first row of thin film transistors arranged along the first direction and a second row of thin film transistors arranged along the first direction, and the first row of thin film transistors and the second row of thin film transistors are spaced apart from each other along the second direction; between any two adjacent thin film transistors belonging to the first row of thin film transistors, is arranged one thin film transistor belonging to the second row of thin film transistors.
5 . The display panel according to claim 1 , wherein for the three thin film transistors in the same pixel structure, connecting lines between every two of centers of the second vias in the three thin film transistors is in a triangle.
6 . The display panel according to claim 1 , wherein for any two adjacent pixel structures in the plurality of pixel structures, the two adjacent pixel structures are referred to as a first pixel structure and a second pixel structure, respectively, and at least one data line is between the second via in the thin film transistor of the first pixel structure closest to the second pixel structure and the second via in the thin film transistor of the second pixel structure closest to the first pixel structure.
7 . The display panel according to claim 1 , wherein the gate, the drain, the source and the active layer are arranged in different layers, respectively; an orthographic projection of the gate on the base substrate at least partially overlaps any one of the orthographic projection of the drain on the base substrate, the orthographic projection of the source on the base substrate and the orthographic projection of the active layer on the base substrate.

Description

TECHNICAL FIELD The present disclosure belongs to the field of display technology, and particularly relates to a thin film transistor and a display panel. BACKGROUND At present, with the development of virtual reality technology and augmented reality technology, the demand for a display panel with ultra-high pixel density (PPI) is increasing. That is, more and more pixel structures are arranged in a unit area, and accordingly, more and more thin film transistors of the pixel structures are required to be arranged in the unit area. An area occupied by the thin film transistor in a plane is large at present, which is difficult to meet the requirements on pixels of the display panel with ultra-high PPI. SUMMARY The present disclosure aims to solve at least one technical problem in the prior art and provides a thin film transistor and a display panel, which can reduce the area occupied by the thin film transistor in a plane. In a first aspect, a technical solution to the technical problem according to the present disclosure is a thin film transistor, including a base substrate, and a drain, a source and an active layer on the base substrate, where the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other. In some embodiments, the thin film transistor further includes a gate, and the gate, the drain, the source and the active layer are arranged in different layers, respectively; an orthographic projection of the gate on the base substrate at least partially overlaps any one of the orthographic projection of the drain on the base substrate, the orthographic projection of the source on the base substrate and the orthographic projection of the active layer on the base substrate. In some embodiments, the drain is on a side of the source close to the base substrate, and the gate is on a side of the source away from the base substrate. In some embodiments, the thin film transistor further includes an interlayer insulating layer between the source and the drain, where the thin film transistor is provided with a first via penetrating through the source and the interlayer insulating layer, and an orthographic projection of the first via on the base substrate is within the orthographic projection of the drain on the base substrate; and where the active layer includes a planar part and a recessed part connected to the planar part; the planar part is on a side of the source away from the drain, and is connected to the source; the recessed part is connected to a part of the planar part at the first via, and the recessed part is concave towards the drain along an inner wall of the first via and is connected to the drain. In some embodiments, a via diameter of the inner wall of the first via gradually decreases in a direction from the source to the drain; and an orthographic projection of a bottom of the recessed part connected to the drain on the base substrate is within an orthographic projection, on the base substrate, of an end aperture of the first via far away from the base substrate. In some embodiments, the gate includes a main body part and a protrusion part connected to the main body part, where the main body part is on a side of the planar part away from the source, and the protrusion part is in a recessed accommodation space defined by the recessed part and the main body part; and the thin film transistor further includes a gate insulating layer, and the gate insulating layer including a first part between the main body part and the planar part and a second part between the protrusion part and the recessed part. In some embodiments, the orthographic projection of the source on the base substrate covers the orthographic projections of the drain and the active layer on the base substrate. In some embodiments, the thin film transistor further includes a gate, a connecting electrode, an interlayer insulating layer and a first insulating layer, the first insulating layer is on a side of the gate away from the base substrate, the interlayer insulating layer is between the source and the drain, and the connecting electrode is on a side of the first insulating layer away from the gate; and the thin film transistor is provided with a second via penetrating through the interlayer insulating layer and the first insulating layer, and the connecting electrode is connected to the source through the second via. In some embodiments, an orthographic projection of the second via on the base substrate has no overlapping region with each of orthographic projections of the gate and the drain on the base substrate. In some embodiments, the active layer is a metal oxide active layer. In a second aspect, the present disclosure further provides a display panel including a plurality of t