US-12628380-B2 - Thin film transistor and display apparatus comprising the same

US12628380B2US 12628380 B2US12628380 B2US 12628380B2US-12628380-B2

Abstract

A thin film transistor comprises an active layer; and a gate electrode spaced apart from the active layer to at least partially overlap the active layer in a plan view. The active layer includes a channel area that is overlapped by the gate electrode in the plan view; a source area connected to one side of the channel area without being overlapped by the gate electrode in the plan view; and a drain area connected to the other side of the channel area without being overlapped by the gate electrode in the plan view. The source area and the drain area are spaced apart from each other with the channel area interposed therebetween. The active layer includes a first source conductorization control area and a first drain conductorization control area, which are spaced apart from each other. The first source conductorization control area corresponds to at least a portion of the channel area in the plan view, and the first drain conductorization control area corresponds to at least a portion of the channel area in the plan view.

Inventors

Jaeyoon PARK
Jinwon Jung
Hyeonjoo SEUL
Sungju Choi
Dongyeon KANG

Assignees

LG DISPLAY CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20231016
Priority Date: 20221209

Claims (20)

1 . A thin film transistor, comprising: an active layer; and a gate electrode spaced apart from the active layer to at least partially overlap the active layer in a plan view, wherein the active layer includes: a channel area that is overlapped by the gate electrode in the plan view; a source area connected to one side of the channel area without being overlapped by the gate electrode in the plan view; and a drain area connected to another side of the channel area without being overlapped by the gate electrode in the plan view, wherein the source area and the drain area are spaced apart from each other with the channel area interposed therebetween, wherein the active layer includes a first source conductorization control area and a first drain conductorization control area, which are spaced apart from each other, wherein the first source conductorization control area corresponds to at least a portion of the channel area in the plan view, wherein the first drain conductorization control area corresponds to at least a portion of the channel area in the plan view, wherein the active layer includes a first active layer, wherein the first active layer is in at least a portion of the channel area, at least a portion of the source area, and at least a portion of the drain area, and wherein the first active layer in the first source conductorization control area has a thickness smaller than that of the first active layer in the channel area except the first source conductorization control area and the first drain conductorization control area.
2 . The thin film transistor of claim 1 , wherein the first drain conductorization control area is on a first line that is a shortest line connecting the source area with the drain area across the first source conductorization control area.
3 . The thin film transistor of claim 1 , wherein the active layer is absent at least at a portion of the first source conductorization control area and the first drain conductorization control area.
4 . The thin film transistor of claim 1 , wherein the first active layer is absent at least at a portion of the first source conductorization control area and the first drain conductorization control area.
5 . The thin film transistor of claim 1 , wherein the active layer further includes a second active layer on the first active layer.
6 . The thin film transistor of claim 5 , wherein the second active layer is in the entire channel area, the entire source area, and the entire drain area.
7 . The thin film transistor of claim 5 , wherein the second active layer is in the first source conductorization control area and the first drain conductorization control area.
8 . The thin film transistor of claim 7 , wherein at least a portion of the second active layer is in contact with a side of the first active layer in the first source conductorization control area and the first drain conductorization control area.
9 . The thin film transistor of claim 5 , wherein the second active layer includes a third oxide semiconductor layer and a fourth oxide semiconductor layer on the third oxide semiconductor layer.
10 . The thin film transistor of claim 9 , wherein at least a portion of the first active layer is in contact with at least a portion of the third oxide semiconductor layer in the first source conductorization control area and the first drain conductorization control area.
11 . The thin film transistor of claim 1 , wherein the first active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.
12 . The thin film transistor of claim 11 , wherein the active layer further includes a second active layer on the first active layer, and wherein at least a portion of the second active layer is in contact with at least one of the first oxide semiconductor layer and the second oxide semiconductor layer in the first source conductorization control area and the first drain conductorization control area.
13 . The thin film transistor of claim 1 , wherein, in the plan view, the first source conductorization control area is disposed in the channel area to a boundary between the channel area and the source area, and the first source conductorization control area does not extend into the source area.
14 . The thin film transistor of claim 1 , wherein, in the plan view, the first drain conductorization control area is disposed in the channel area to a boundary between the channel area and the drain area, and the first drain conductorization control area does not extend into the drain area.
15 . The thin film transistor of claim 1 , wherein, in the plan view, the first source conductorization control area is in the channel area and in the source area to extend across a boundary between the channel area and the source area.
16 . The thin film transistor of claim 15 , wherein the first source conductorization control area extends 0.5 μm to 5 μm into the source area.
17 . The thin film transistor of claim 1 , wherein, in the plan view, the first drain conductorization control area is in the channel area and in the drain area to extend across a boundary between the channel area and the drain area.
18 . The thin film transistor of claim 17 , wherein the first drain conductorization control area extends 0.5 μm to 5 μm into the drain area.
19 . The thin film transistor of claim 1 , wherein, in the plan view, the first source conductorization control area does not extend across a boundary between the channel area and the source area.
20 . The thin film transistor of claim 19 , wherein a shortest distance between the first source conductorization control area and the boundary between the channel area and the source area ranges from 0.5 μm to 1.5 μm.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority of the Korean Patent Application No. 10-2022-0171711 filed on Dec. 9, 2022, which is hereby incorporated by reference as if fully set forth herein. BACKGROUND Technical Field The present disclosure relates to a thin film transistor and a display apparatus comprising the same. Discussion of the Related Art Transistors are widely used as switching devices or driving devices in the field of electronic apparatuses. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, the thin film transistor is widely used as a switching device of a display apparatus such as a liquid crystal display apparatus or an organic light emitting apparatus. Based on a material constituting the active layer, the thin film transistor may be categorized into an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor thin film transistor in which oxide semiconductor is used as an active layer. Because amorphous silicon may be deposited in a short time to form an active layer, an amorphous silicon thin film transistor (a-Si TFT) has advantages in that a manufacturing process time is short and a production cost is low. On the other hand, the amorphous silicon thin film transistor has a drawback in that it is restrictively used for an active matrix organic light emitting diode (AMOLED) because a current driving capacity is not good due to low mobility and there is a change in a threshold voltage. A polycrystalline silicon thin film transistor (poly-Si TFT) is made by depositing amorphous silicon and crystallizing the deposited amorphous silicon. Because a process of manufacturing the polycrystalline silicon thin film transistor needs a step of crystallizing the amorphous silicon, a manufacturing cost is increased due to the increased number of the process steps. Because crystallization is performed at a high process temperature, it is difficult to apply the polycrystalline silicon thin film transistor to a large-sized display apparatus. Also, it is difficult to make sure of uniformity of the polycrystalline silicon thin film transistor due to polycrystalline characteristics. An oxide constituting an active layer of an oxide semiconductor thin film transistor may be grown at a relatively low temperature, and the oxide semiconductor thin film transistor has high mobility, and has a large resistance change in accordance with an oxygen content, whereby desired properties may be easily obtained. Further, in view of the properties of the oxide and because an oxide semiconductor is transparent, the oxide semiconductor thin film transistor may be favorable in a transparent display. In the case of the oxide semiconductor thin film transistor, selective conductorization for an oxide semiconductor layer may be required, and in this case, it is important to control a conductorization area formed in the oxide semiconductor layer and a conductorization permeation depth. Therefore, techniques for controlling the conductorization area and the conductorization permeation depth are being studied. SUMMARY Accordingly, embodiments of the present disclosure are directed to a thin film transistor and a display apparatus comprising the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. An aspect of the present disclosure is to provide a thin film transistor in which an active layer includes a pattern so that a conductorization permeation depth is controlled even though a channel area has a large width. Another aspect of the present disclosure is to provide a thin film transistor in which an active layer includes a pattern so that a threshold voltage is prevented or suppressed from being shifted in a negative (−) direction even though a channel area has a large width. Still another aspect of the present disclosure is to provide a thin film transistor in which an active layer includes a pattern to improve reliability. Further still another aspect of the present disclosure is to provide a display apparatus comprising the above thin film transistor. Additional features and aspects will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in the written description, or derivable therefrom, and the claims hereof as well as the appended drawings. To achieve these and other aspects of the inventive concepts, as embodied and broadly described herein, a thin film transistor comprises an active layer; and a gate electrode spaced apart from the active layer to at le