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US-12628381-B2 - Wakeup-free ferroelectric memory device

US12628381B2US 12628381 B2US12628381 B2US 12628381B2US-12628381-B2

Abstract

The present disclosure relates to a method for forming a ferroelectric memory device. The method includes forming a dielectric layer over a semiconductor substrate and forming a first conductive layer over the dielectric layer. The first conductive layer has a first overall electronegativity. A ferroelectric layer is formed on the first conductive layer. The ferroelectric layer has a second overall electronegativity less than or equal to the first overall electronegativity. A second conductive layer is formed on the ferroelectric layer. The second conductive layer has a third overall electronegativity greater than or equal to the second overall electronegativity. The second conductive layer, the ferroelectric layer, and the first conductive layer are etched to form a polarization switching structure. An ILD layer is formed over the polarization switching structure, and a planarization process is performed on the ILD layer. A first conductive via is formed over the polarization switching structure.

Inventors

  • Mickey Hsieh
  • Chun-Yang Tsai
  • Kuo-Ching Huang
  • Kuo-Chi Tu
  • Pili Huang
  • Cheng-Jun Wu
  • Chao-Yang Chen

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260512
Application Date
20230223

Claims (20)

  1. 1 . A method for forming a ferroelectric memory device, comprising: forming a dielectric layer over a semiconductor substrate; forming a first conductive layer over the dielectric layer, wherein the first conductive layer has a first overall electronegativity; forming a ferroelectric layer on the first conductive layer, wherein the ferroelectric layer has a second overall electronegativity that is less than or equal to the first overall electronegativity; forming a second conductive layer on the ferroelectric layer, wherein the second conductive layer has a third overall electronegativity that is greater than or equal to the second overall electronegativity; etching the second conductive layer, the ferroelectric layer, and the first conductive layer to form a polarization switching structure over the semiconductor substrate; depositing an interlayer dielectric (ILD) layer over the polarization switching structure; performing a planarization process on the ILD layer to form an ILD structure surrounding the polarization switching structure; and forming a first conductive via over the polarization switching structure.
  2. 2 . The method of claim 1 , wherein the first conductive layer, the second conductive layer, and the ferroelectric layer have maximum widths that are substantially equal after being etched.
  3. 3 . The method of claim 1 , wherein the first conductive layer and the second conductive layer respectively comprise polysilicon having an n-type doping or polysilicon having a p-type doping.
  4. 4 . The method of claim 1 , wherein the first conductive layer and the second conductive layer respectively comprise iridium.
  5. 5 . The method of claim 1 , further comprising: forming a sacrificial layer over the second conductive layer prior to depositing the ILD layer; and removing the sacrificial layer from over the polarization switching structure after performing the planarization process and before forming the first conductive via.
  6. 6 . The method of claim 1 , further comprising: forming one or more dielectric spacers along opposing sides of the polarization switching structure; and forming the ILD layer along one or more sidewalls of the one or more dielectric spacers.
  7. 7 . The method of claim 6 , wherein the one or more dielectric spacers continuously extend from vertically below a bottom of the polarization switching structure to vertically above a top of the polarization switching structure.
  8. 8 . The method of claim 1 , further comprising: forming a semiconductor device on the semiconductor substrate, wherein the semiconductor device comprises a gate electrode disposed over the semiconductor substrate; and wherein a first conductive via is configured to electrically couple the gate electrode of the semiconductor device to the polarization switching structure.
  9. 9 . A method for forming a ferroelectric memory device, comprising: forming a dielectric layer over a substrate; forming a ferroelectric device stack over the dielectric layer, the ferroelectric device stack comprising a first conductive layer over the dielectric layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer, wherein the ferroelectric layer has a smaller electronegativity than the first conductive layer and the second conductive layer; forming a processing layer over the second conductive layer; etching the ferroelectric device stack and the processing layer to form a polarization switching structure covered by a sacrificial gate; forming an interlayer dielectric (ILD) structure on opposing sides of the polarization switching structure and the sacrificial gate; removing the sacrificial gate after forming the ILD structure to form a gate recess; and forming a gate electrode within the gate recess.
  10. 10 . The method of claim 9 , further comprising: forming one or more sidewall spacers along the opposing sides of the polarization switching structure and the sacrificial gate prior to forming the ILD structure, wherein the one or more sidewall spacers laterally separate the polarization switching structure and the sacrificial gate from the ILD structure.
  11. 11 . The method of claim 10 , wherein a bottom surface of the gate electrode is disposed vertically between the substrate and an upper surface of the one or more sidewall spacers.
  12. 12 . The method of claim 9 , wherein the second conductive layer and the gate electrode have maximum widths that are substantially equal.
  13. 13 . The method of claim 9 , wherein the polarization switching structure has a surface area that is between approximately 1 square nanometer and approximately 100 square micrometers.
  14. 14 . The method of claim 9 , wherein the second conductive layer is completely confined above a top surface of the ferroelectric layer after etching the ferroelectric device stack.
  15. 15 . A method for forming a ferroelectric memory device, comprising: forming a dielectric over a substrate; forming a ferroelectric device stack over the dielectric; etching the ferroelectric device stack to form a polarization switching structure over the dielectric, the polarization switching structure comprising a ferroelectric structure disposed between a first conductive structure and a second conductive structure, wherein the ferroelectric structure has a smaller electronegativity than the first conductive structure and the second conductive structure; wherein the first conductive structure has a first thickness that is in a first range of between approximately 0.1 nanometer and approximately 1,000 nanometers; wherein the ferroelectric structure has a second thickness that is in a second range of between approximately 1 nanometer and approximately 100 nanometers; and wherein opposite outermost sidewalls of the first conductive structure, the ferroelectric structure, and the second conductive structure are separated by distances that are substantially the same.
  16. 16 . The method of claim 15 , further comprising: forming a semiconductor device on the substrate, wherein the semiconductor device comprises a gate electrode disposed over the substrate; and forming a conductive interconnect over the substrate, the conductive interconnect configured to electrically couple the gate electrode of the semiconductor device to the polarization switching structure.
  17. 17 . The method of claim 15 , wherein the first conductive structure and the second conductive structure respectively comprise doped polysilicon.
  18. 18 . The method of claim 15 , further comprising: forming a first electrode to contact an upper surface of a first conductive via over the substrate; forming the first conductive structure to contact an upper surface of the first electrode, wherein an overall electronegativity of the first conductive structure is greater than or equal to an overall electronegativity of the first electrode; forming a second electrode to contact an upper surface of the second conductive structure; and forming a second conductive via to contact an upper surface of the second electrode, wherein an overall electronegativity of the second conductive structure is greater than or equal to an overall electronegativity of the second electrode.
  19. 19 . The method of claim 18 , wherein an overall electronegativity of the first conductive via is less than or equal to the overall electronegativity of the second conductive structure.
  20. 20 . The method of claim 15 , wherein one or more of the first conductive structure or the second conductive structure comprise tungsten.

Description

REFERENCE TO RELATED APPLICATIONS This Application is a Continuation of U.S. application Ser. No. 17/117,711, filed on Dec. 10, 2020, which is a Divisional of U.S. application Ser. No. 16/405,058, filed on May 7, 2019 (now U.S. Pat. No. 10,879,391, issued on Dec. 29, 2020). The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety. BACKGROUND Many modern day electronic devices include non-volatile memory. Non-volatile memory is electronic memory that is able to store data in the absence of power. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiments of a first integrated chip (IC) comprising a first wakeup-free ferroelectric memory device. FIG. 2 illustrates a magnified cross-sectional view of some embodiments of the device gate stack of FIG. 1. FIG. 3 illustrates a top view of some embodiments of the first conductive structure, the ferroelectric structure, and the second conductive structure removed from their stacked orientation in FIG. 1 and disposed next to one another. FIG. 4 illustrates a cross-sectional view of some more detailed embodiments of the first IC of FIG. 1. FIG. 5 illustrates a cross-sectional view of some other embodiments of the first IC of FIG. 4. FIG. 6 illustrates a cross-sectional view of some other embodiments of the first IC of FIG. 4. FIG. 7 illustrates a cross-sectional view of some embodiments of a second IC comprising a second wakeup-free ferroelectric memory device. FIG. 8 illustrates a cross-sectional view of some other embodiments of the second IC of FIG. 7. FIG. 9 illustrates a cross-sectional view of some other embodiments of the second IC of FIG. 7. FIG. 10 illustrates a cross-sectional view of some other embodiments of the second IC of FIG. 9. FIGS. 11-20 illustrate a series of cross-sectional views of some embodiments for forming the first IC of FIG. 5. FIG. 21 illustrates a flowchart of some embodiments of a method for forming an IC comprising a front-end-of-line wakeup-free ferroelectric memory device. FIG. 22 illustrates a flowchart of some embodiments of a method for forming an IC comprising a back-end-of-line wakeup-free ferroelectric memory device. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some ferroelectric memory (e.g., ferroelectric random-access memory (FeRAM)) comprises a ferroelectric memory cell. The ferroelectric memory cell comprises a ferroelectric structure disposed between a first electrode and a second electrode. In other embodiments, the ferroelectric structure may be disposed between a gate electrode and a semiconductor substrate (e.g., ferroelectric field-effect transistor (FeFET). The ferroelectric structure is configured to switch between polarization states to store data (e.g., binary “0” and “1”).