US-12628382-B2 - Interfacial dual passivation layer for a ferroelectric device and methods of forming the same

US12628382B2US 12628382 B2US12628382 B2US 12628382B2US-12628382-B2

Abstract

A semiconductor structure includes, from bottom to top or from top to bottom, a gate electrode, a ferroelectric dielectric layer, a metal-rich metal oxide layer, a dielectric metal nitride layer, and a metal oxide semiconductor layer. A ferroelectric field effect transistor may be provided by forming a source region and a drain region on the metal oxide semiconductor layer. The metal-rich metal oxide layer and the dielectric metal nitride layer homogenize and stabilize the interface between the ferroelectric dielectric layer and the metal oxide semiconductor layer, and reduce excess oxygen atoms at the interface, thereby improving switching characteristics of the ferroelectric field effect transistor.

Inventors

Jiamin Wang
Blanka Magyari-Kope
Chris LIU
Ashwathi Iyer

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date: 20260512
Application Date: 20240627

Claims (20)

1 . A method of forming a semiconductor structure, comprising: forming a gate electrode in, or on, an upper portion of an insulating material layer over a substrate; depositing a ferroelectric dielectric material layer on the gate electrode; forming a metal-rich hafnium oxide layer on the ferroelectric dielectric material layer; forming a stoichiometric HfN layer on the metal-rich metal oxide layer; depositing a metal oxide semiconductor material layer over the stoichiometric HfN layer; patterning the metal oxide semiconductor material layer, the stoichiometric HfN layer, the metal-rich hafnium oxide layer, and the ferroelectric dielectric material layer; and forming a source region and a drain region on a patterned portion of the metal oxide semiconductor material layer.
2 . The method of claim 1 , wherein the stoichiometric HfN layer is formed by nitridating an upper portion of the metal-rich hafnium oxide layer.
3 . The method of claim 1 , wherein the metal-rich hafnium oxide layer is formed by depositing a hafnium layer on the ferroelectric dielectric material layer, wherein atoms of the metallic element are oxidized by combining with oxygen atoms within the ferroelectric dielectric material layer.
4 . The method of claim 1 , wherein: the metal-rich hafnium oxide layer is formed as a non-stoichiometric hafnium oxide having a thickness that is not greater than a distance of a full bond between a fully bonded pair of a hafnium atom and an oxygen atom; the stoichiometric HfN layer has a thickness in a range from 0.2 nm to 0.4 nm; and an oxygen excess interface region in which oxygen deficiency is eliminated is formed within the combination of the stoichiometric HfN layer and the metal-rich hafnium oxide layer between the metal oxide semiconductor layer and the ferroelectric dielectric layer.
5 . The method of claim 4 , wherein: a subset of hafnium atoms within a combination of the stoichiometric HfN layer and the metal-rich hafnium oxide layer has first interatomic bonding at a first Hf—O interatomic bonding distance that provides said full bond with a respective surface oxygen atom selected from surface oxygen atoms of the ferroelectric dielectric layer due to proximity of the subset of hafnium atoms to the ferroelectric dielectric layer, and has second interatomic bondings at a second Hf—O interatomic bonding distance that is greater than the first Hf—O interatomic bonding distance and provides a weaker bonding than said full bond with a respective surface oxygen atom selected from the surface oxygen atoms of the metal oxide semiconductor layer due to proximity of the subset of hafnium atoms to the surface oxygen atoms of the metal oxide semiconductor layer by virtue of the stoichiometric HfN layer having the thickness in the range from 0.2 nm to 0.4 nm; and the oxygen excess interface region is formed due to presence of the first interatomic bondings and the second interatomic bondings within the subset of hafnium atoms.
6 . The method of claim 1 , wherein the source region and the drain region are formed on a respective segment of a top surface of the metal oxide semiconductor material layer in areas that are laterally offset from an area of the gate electrode.
7 . The method claim 1 , wherein the metal oxide semiconductor material layer is formed by depositing a semiconductor material that is free of hafnium.
8 . The method of claim 1 , further comprising: forming a recess region in an upper portion of the insulating material layer; and depositing a conductive material in the recess region and removing portions of the conductive material from outside the recess region, wherein a remaining portion of the conductive material comprises the gate electrode, and wherein the ferroelectric dielectric material layer is deposited on a top surface of the insulating material layer.
9 . The method of claim 1 , wherein the metal oxide semiconductor material layer, the stoichiometric HfN layer, the metal-rich hafnium oxide layer, and the ferroelectric dielectric material layer are patterned such that remaining portions of the metal oxide semiconductor material layer, the stoichiometric HfN layer, the metal-rich hafnium oxide layer, and the ferroelectric dielectric material layer have sidewalls that are vertically coincident among one another.
10 . A method of forming a semiconductor structure, comprising: depositing a metal oxide semiconductor material layer on an insulating material layer over a substrate; forming a stoichiometric HfN layer on the metal oxide semiconductor material layer; forming a metal-rich hafnium oxide layer over the stoichiometric HfN layer; depositing a ferroelectric dielectric material layer over the metal-rich hafnium oxide layer; depositing a gate electrode material layer on the ferroelectric dielectric material layer; patterning the gate electrode material layer, the ferroelectric dielectric material layer, the metal-rich hafnium oxide layer, the stoichiometric HfN layer, and the metal oxide semiconductor material layer; and forming a source region and a drain region on a patterned portion of the metal oxide semiconductor material layer.
11 . The method of claim 10 , wherein the metal-rich hafnium oxide layer is formed by depositing a hafnium layer on the stoichiometric HfN layer, wherein hafnium atoms of the hafnium layer are oxidized by combining with oxygen atoms within the ferroelectric dielectric material layer that is subsequently deposited on the hafnium layer.
12 . The method of claim 10 , wherein the stoichiometric HfN layer includes a continuous monolayer of stoichiometric HfN.
13 . The method of claim 10 , wherein: the metal-rich hafnium oxide layer is formed as a non-stoichiometric hafnium oxide having a thickness that is not greater than a distance of a full bond between a fully bonded pair of a hafnium atom and an oxygen atom; the stoichiometric HfN layer has a thickness in a range from 0.2 nm to 0.4 nm; and an oxygen excess interface region in which oxygen deficiency is eliminated is formed within the combination of the stoichiometric HfN layer and the metal-rich hafnium oxide layer between the metal oxide semiconductor layer and the ferroelectric dielectric layer.
14 . The method of claim 13 , wherein: a subset of hafnium atoms within a combination of the stoichiometric HfN layer and the metal-rich hafnium oxide layer has first interatomic bonding at a first Hf—O interatomic bonding distance that provides said full bond with a respective surface oxygen atom selected from surface oxygen atoms of the ferroelectric dielectric layer due to proximity of the subset of hafnium atoms to the ferroelectric dielectric layer, and has second interatomic bondings at a second Hf—O interatomic bonding distance that is greater than the first Hf—O interatomic bonding distance and provides a weaker bonding than said full bond with a respective surface oxygen atom selected from the surface oxygen atoms of the metal oxide semiconductor layer due to proximity of the subset of hafnium atoms to the surface oxygen atoms of the metal oxide semiconductor layer by virtue of the stoichiometric HfN layer having the thickness in the range from 0.2 nm to 0.4 nm; and the oxygen excess interface region is formed due to presence of the first interatomic bondings and the second interatomic bondings within the subset of hafnium atoms.
15 . The method of claim 10 , wherein an average atomic coordination number of the metal-rich hafnium oxide is in a range from 0.5 to 1.8.
16 . A method of forming a semiconductor structure, comprising: sequentially forming, over a substrate and in a forward order or in a reverse order, a gate electrode, a ferroelectric dielectric material layer, a metal-rich hafnium oxide layer, a stoichiometric HfN layer, and a metal oxide semiconductor material layer, wherein the metal-rich hafnium oxide layer is formed as a non-stoichiometric hafnium oxide having a thickness that is not greater than a distance of a full bond between a fully bonded pair of a hafnium atom and an oxygen atom, wherein the stoichiometric HfN layer has a thickness in a range from 0.2 nm to 0.4 nm, and wherein an oxygen excess interface region in which oxygen deficiency is eliminated is formed within the combination of the stoichiometric HfN layer and the metal-rich hafnium oxide layer between the metal oxide semiconductor layer and the ferroelectric dielectric layer; and patterning the ferroelectric dielectric material layer, the metal-rich hafnium oxide layer, the stoichiometric HfN layer, and the metal oxide semiconductor material layer employing at least one photoresist layer and at least one anisotropic etch process.
17 . The method of claim 16 , wherein: a subset of hafnium atoms within a combination of the stoichiometric HfN layer and the metal-rich hafnium oxide layer has first interatomic bonding at a first Hf—O interatomic bonding distance that provides said full bond with a respective surface oxygen atom selected from surface oxygen atoms of the ferroelectric dielectric layer due to proximity of the subset of hafnium atoms to the ferroelectric dielectric layer, and has second interatomic bondings at a second Hf—O interatomic bonding distance that is greater than the first Hf—O interatomic bonding distance and provides a weaker bonding than said full bond with a respective surface oxygen atom selected from the surface oxygen atoms of the metal oxide semiconductor layer due to proximity of the subset of hafnium atoms to the surface oxygen atoms of the metal oxide semiconductor layer by virtue of the stoichiometric HfN layer having the thickness in the range from 0.2 nm to 0.4 nm; and the oxygen excess interface region is formed due to presence of the first interatomic bondings and the second interatomic bondings within the subset of hafnium atoms.
18 . The method of claim 16 , wherein: the ferroelectric dielectric material layer comprises hafnium zirconium oxide; and the metal oxide semiconductor material layer comprises indium gallium zinc oxide.
19 . The method of claim 16 , wherein: a stack of the stoichiometric HfN layer and the metal-rich hafnium oxide layer is formed after formation of the metal oxide semiconductor layer; a surface of the metal oxide semiconductor layer is oxygen-deficient prior to formation of the stack of a dielectric metal nitride layer the metal-rich metal oxide layer; and said oxygen deficiency is elimination due to formation of the oxygen excess interface region upon formation of the stack of the stoichiometric HfN layer and the metal-rich hafnium oxide layer.
20 . The method of claim 16 , wherein the metal oxide semiconductor material layer comprises at least indium, zirconium, and oxygen.

Description

RELATED APPLICATIONS This application is a divisional application of U.S. application Ser. No. 17/228,550 entitled “Interfacial Dual Passivation Layer for a Ferroelectric Device and Methods of Forming the Same,” filed Apr. 5, 2021, which claims the benefit of priority from U.S. Provisional Application No. 63/042,598 entitled “Oxide Semiconductor Device with Enhanced Surface Passivation and Method of Fabricating the Same” filed on Jun. 23, 2020, the entire contents of both of which are hereby incorporated by reference for all purposes. BACKGROUND A ferroelectric material is a material that may have spontaneous nonzero electrical polarization (i.e., non-zero total electrical dipole moment) when the external electrical field is zero. The spontaneous electrical polarization may be reversed by a strong external electric field applied in the opposite direction. The electrical polarization is dependent not only on the external electrical field at the time of measurement, but also on the history of the external electrical field, and thus, has a hysteresis loop. The maximum of the electrical polarization is referred to as saturation polarization. The electrical polarization that remains after an external electrical field that induces saturation polarization is no longer applied (i.e., turned off) is referred to as remnant polarization. The magnitude of the electrical field that needs to be applied in the opposite direction of the remnant polarization in order to achieve zero polarization is referred to as coercive electrical field. For the purposes of forming memory devices, it is generally desirable to have high remnant polarization and high coercive field. High remnant polarization may increase the magnitude of an electrical signal. High coercive field makes the memory devices more stable against perturbations caused by noise-level electrical field and interferences. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a top-down view of a first exemplary structure after formation of a gate electrode in an upper portion of an insulating material layer over a substrate according to a first embodiment of the present disclosure. FIG. 1B is a vertical cross-sectional view of the first exemplary structure along the plane B-B′ of FIG. 1A. FIG. 2 is a vertical cross-sectional view of the first exemplary structure after deposition of a ferroelectric dielectric material layer according to the first embodiment of the present disclosure. FIG. 3 is a vertical cross-sectional view of the first exemplary structure after formation of a metal-rich metal oxide material layer according to the first embodiment of the present disclosure. FIG. 4 is a vertical cross-sectional view of the first exemplary structure after formation of a dielectric metal nitride material layer according to the first embodiment of the present disclosure. FIG. 5 is a vertical cross-sectional view of the first exemplary structure after deposition of a metal oxide semiconductor material layer according to the first embodiment of the present disclosure. FIG. 6A is a top-down view of the first exemplary structure after patterning the metal oxide semiconductor material layer, the dielectric metal nitride material layer, the metal-rich metal oxide material layer, and the ferroelectric dielectric material layer according to the first embodiment of the present disclosure. FIG. 6B is a vertical cross-sectional view of the first exemplary structure along the plane B-B′ of FIG. 6A. FIG. 7A is a top-down view of the first exemplary structure after formation of a source region and a drain region according to the first embodiment of the present disclosure. FIG. 7B is a vertical cross-sectional view of the first exemplary structure along the plane B-B′ of FIG. 7A. FIG. 8A is a top-down view of the first exemplary structure after formation of a contact-level dielectric layer and contact via structures according to the first embodiment of the present disclosure. FIG. 8B is a vertical cross-sectional view of the first exemplary structure along the plane B-B′ of FIG. 8A. FIG. 8C is a vertical cross-sectional view of the first exemplary structure along the plane C-C′ of FIG. 8A. FIG. 9A is a top-down view of an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. FIG. 9B is a vertical cross-sectional view of the first exemplary structure along the plane B-B′ of FIG. 9A. FIG. 10 is a vertical cross-sectional view of a second exemplary structure after deposition of a metal oxide semiconductor material layer on a top surface of an insulating material layer over a