US-12628383-B2 - Transistors having stacked 2D material channel layers and heterogeneous 2D material contacts layers epitaxial to the 2D material channel layers

US12628383B2US 12628383 B2US12628383 B2US 12628383B2US-12628383-B2

Abstract

Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.

Inventors

Kirby MAXEY
Ashish Verma Penumatcha
Carl Naylor
Chelsey DOROW
Kevin O'Brien
Shriram Shivaraman
Tanay Gosavi
Uygar Avci

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260512
Application Date: 20210924

Claims (20)

1 . An apparatus, comprising: a plurality of semiconductor channel layers interleaved with a plurality of gate layers, each of the gate layers comprising a gate electrode layer and a gate dielectric layer, wherein the semiconductor channel layers comprise a first transition metal dichalcogenide comprising a first transition metal of tungsten or molybdenum and a first chalcogen of sulfur or selenium; first contact layers and second contact layers on opposite lateral ends of and epitaxial to the semiconductor channel layers, wherein the first and second contact layers comprise a second transition metal dichalcogenide comprising a second transition metal of niobium or tantalum and a second chalcogen of sulfur; a gate contact coupled to the gate electrode layers; and a source contact coupled to the first contact layers and a drain contact coupled to the second contact layers, wherein one of the first contact layers comprises a first portion on a first semiconductor channel layer of the semiconductor channel layers and within a first recess between first and second gate dielectric layers on opposite sides of the first semiconductor channel layer, another one of the first contact layers comprises a second portion on a second semiconductor channel layer of the semiconductor channel layers and within a second recess between third and fourth gate dielectric layers on opposite sides of the second semiconductor channel layer, and the first portion and the second portion are separated by and are in contact with a third portion of the source contact that separates the first portion and the second portion.
2 . The apparatus of claim 1 , wherein the gate electrode layers comprise ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, or aluminum.
3 . The apparatus of claim 1 , wherein the gate dielectric layers comprise hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, lead scandium tantalum oxide, or lead zinc niobate.
4 . The apparatus of claim 1 , wherein the gate contact comprises a polycrystalline material.
5 . The apparatus of claim 1 , wherein the source contact and the drain contact comprise gold, silver, platinum, or palladium.
6 . The apparatus of claim 1 , further comprising: a power supply; and an integrated circuit die coupled to the power supply, the integrated circuit die comprising the semiconductor channel layers, the gate layers, the first contact layers, the second contact layers, the gate contact, the source contact, and the drain contact.
7 . An apparatus, comprising: a plurality of semiconductor channel layers interleaved with a plurality of gate layers, each of the gate layers comprising a gate electrode layer and a gate dielectric layer, wherein the semiconductor channel layers comprise a first transition metal dichalcogenide comprising a first transition metal of tungsten or molybdenum and a first chalcogen of sulfur or selenium; first contact layers and second contact layers on opposite lateral ends of and epitaxial to of the semiconductor channel layers, wherein the first and second contact layers comprise a second transition metal dichalcogenide comprising a second transition metal of tungsten or molybdenum and a second chalcogen of tellurium; a gate contact coupled to the gate electrode layers; and a source contact coupled to the first contact layers and a drain contact coupled to the second contact layers, wherein one of the first contact layers comprises a first portion on a first semiconductor channel layer of the semiconductor channel layers and within a first recess between first and second gate dielectric layers on opposite sides of the first semiconductor channel layer, another one of the first contact layers comprises a second portion on a second semiconductor channel layer of the semiconductor channel layers and within a second recess between third and fourth gate dielectric layers on opposite sides of the second semiconductor channel layer, and the first portion and the second portion are separated by and are in contact with a third portion of the source contact that separates the first portion and the second portion.
8 . The apparatus of claim 7 , wherein the gate electrode layers comprise ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, or aluminum.
9 . The apparatus of claim 7 , wherein the gate dielectric layers comprise hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, lead scandium tantalum oxide, or lead zinc niobate.
10 . The apparatus of claim 7 , wherein the gate contact comprises a polycrystalline material.
11 . The apparatus of claim 7 , wherein the source contact and the drain contact comprise gold, silver, platinum, or palladium.
12 . The apparatus of claim 7 , further comprising: a power supply; and an integrated circuit die coupled to the power supply, the integrated circuit die comprising the semiconductor channel layers, the gate layers, the first contact layers, the second contact layers, the gate contact, the source contact, and the drain contact.
13 . An apparatus, comprising: a plurality of semiconductor channel layers interleaved with a plurality of gate layers, each of the plurality of gate layers comprising a gate electrode layer and a gate dielectric layer, wherein the semiconductor channel layers comprise a first 2D material, the first 2D material comprising a first compound of a first metal and a first chalcogen and having a first crystalline phase; first contact layers and second contact layers on opposite lateral ends of and epitaxial to of the semiconductor channel layers, wherein the first and second contact layers comprise a second 2D material, the second 2D material comprising a second compound of a second metal and a second chalcogen and having a second crystalline phase, wherein at least one of the second metal, the second chalcogen, or the second crystalline phase is different with respect to the first metal, the first chalcogen, or the first crystalline phase, respectively; a gate contact coupled to the gate electrode layers; and a source contact coupled to the first contact layers and a drain contact coupled to the second contact layers, wherein one of the first contact layers comprises a first portion on a first semiconductor channel layer of the semiconductor channel layers and within a first recess between first and second gate dielectric layers on opposite sides of the first semiconductor channel layer, another one of the first contact layers comprises a second portion on a second semiconductor channel layer of the semiconductor channel layers and within a second recess between third and fourth gate dielectric layers on opposite sides of the second semiconductor channel layer, and the first portion and the second portion are separated by and are in contact with a third portion of the source contact that separates the first portion and the second portion.
14 . The apparatus of claim 13 , wherein the first metal comprises indium, the first chalcogen comprises selenium, the second metal comprises one of niobium, tantalum, tungsten, or molybdenum, and the second chalcogen comprises one of sulfur or tellurium.
15 . The apparatus of claim 13 , wherein the first metal and the second metal comprise molybdenum, the first chalcogen and the second chalcogen comprises tellurium, the first crystalline phase is a hexagonal phase, and the second crystalline phase is a tetragonal phase.
16 . The apparatus of claim 13 , wherein the first metal comprises one of molybdenum or tungsten, the first chalcogen comprises one of sulfur or selenium, and the second metal comprises niobium or the second chalcogen comprises tellurium.
17 . The apparatus of claim 13 , wherein the gate electrode layers comprise ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, or aluminum.
18 . The apparatus of claim 13 , wherein the gate dielectric layers comprise hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, lead scandium tantalum oxide, or lead zinc niobate.
19 . The apparatus of claim 13 , wherein the gate contact comprises a polycrystalline material.
20 . The apparatus of claim 13 , wherein the source contact and the drain contact comprise gold, silver, platinum, or palladium.

Description

BACKGROUND Demand for integrated circuits (ICs) in electronic applications has motivated research into new materials for advanced transistor devices. For example, materials to replace the silicon channel of traditional transistors are being sought. In particular, scaling silicon to extremely small channel lengths and thicknesses is unworkable as the behavior of the silicon material changes at such dimensions. Replacement channel materials include 2D materials inclusive of transition metal dichalcogenides (TMD) and similar materials. However, challenges arise in deploying 2D materials. For example, 2D transistors suffer from contact resistances that are at best an order of magnitude higher than what is needed for high-performance devices. Such high contact resistances are due to the inability to selectively dope contact regions and other concerns. Notably, 2D materials have the promise of outperforming silicon and III-V materials for gate lengths of less than 10 nm due to decreased short channel effects but current shortcomings must be resolved. It is desirable to deploy transistors with 2D channel materials for improved device performance It is with respect to these and other considerations that the present improvements have been needed. Such improvements may become critical as the need for higher performance integrated circuit electronic devices becomes more widespread. BRIEF DESCRIPTION OF THE DRAWINGS The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures: FIG. 1A illustrates a top down view of an exemplary transistor structure having semiconductor channel layers and contact layers of heterogeneous 2D materials; FIG. 1B provides illustration of a cross-sectional side view of the transistor structure of FIG. 1A taken along the channel thereof; FIG. 1C provides illustration of a cross-sectional side view of the transistor structure of FIG. 1A taken across the gate thereof; FIG. 2 illustrates a flow diagram illustrating an example process for fabricating transistor structures having semiconductor channel layers and contact layers of heterogeneous 2D materials; FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A illustrate top down views of example transistor structures as particular fabrication operations of the process of FIG. 2; FIGS. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B illustrate cross-sectional side views of the transistor structures of FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A taken along the channel thereof; FIGS. 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, and 17C illustrate cross-sectional side views of the transistor structures of FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A taken across the gate thereof; FIG. 18 is an illustrative diagram of a mobile computing platform employing a device including a transistor having semiconductor channel layers and contact layers of heterogeneous 2D materials; and FIG. 19 is a functional block diagram of a computing device, all arranged in accordance with at least some implementations of the present disclosure. DETAILED DESCRIPTION One or more embodiments or implementations are now described with reference to the enclosed figures. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may also be employed in a variety of other systems and applications other than what is described herein. Reference is made in the following detailed description to the accompanying drawings, which form a part hereof, wherein like numerals may designate like parts throughout to indicate corresponding or analogous elements. It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, it is to be understood that other embodiments may be utilized, and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, botto