US-12628384-B2 - Enhanced-shaped extension region(s) for gate-all-around (GAA) field effect transistor (FET) device, and related fabrication methods

US12628384B2US 12628384 B2US12628384 B2US 12628384B2US-12628384-B2

Abstract

Enhanced-shaped extension region for gate-all-around (GAA) field-effect transistor (FET) devices and related fabrication methods are disclosed. The GAA FET device includes an extension region of semiconductor material coupled from the respective channel to the source/drain region to facilitate forming a conductive channel between the source and the drain regions when the GAA FET device is activated. The area of the extension region between the source/drain regions and the channel forms a series resistance between source/drain regions and the channel. To reduce channel parasitic resistance, the extension region of the GAA FET device has an enhanced extension portion that has an extended height orthogonal to the channel direction. The extension region with its enhanced extension portion has reduced resistance as compared to an extension region not containing the enhanced extension portion, thus reducing channel parasitic resistance of the GAA FET device for improved performance.

Inventors

Peijie Feng
Yan Sun
Shreesh Narasimha

Assignees

QUALCOMM INCORPORATED

Dates

Publication Date: 20260512
Application Date: 20230505

Claims (20)

1 . A gate-all-around (GAA) field effect transistor (FET) device, comprising: a first electrode on a substrate; a second electrode on the substrate; a channel extending in a first direction between the first electrode and the second electrode, the channel having a first width in the first direction, the channel comprising: one or more channel structures each having a first height in a second direction orthogonal to the first direction; a gate surrounding the channel; one or more first extension regions each extending from a channel structure of the one or more channel structures to the first electrode; and the one or more first extension regions each comprising: one or more first enhanced extension portions each having a second height in the second direction greater than the first height; wherein: the gate comprises one or more gate structures each having a third height in the second direction and each disposed adjacent to at least one channel structure of the one or more channel structures in the second direction; and the gate further comprises: one or more inner spacers each adjacent to a gate structure of the one or more gate structures and each having a fourth height directly adjacent to the gate structure that is less than the third height.
2 . The GAA FET device of claim 1 , further comprising: one or more second extension regions each extending from a channel structure of the one or more channel structures to the second electrode; and the one or more second extension regions each having the first height.
3 . The GAA FET device of claim 1 , further comprising: one or more second extension regions each extending from a channel structure of the one or more channel structures to the second electrode; and the one or more second extension regions each comprising: one or more second enhanced extension portions each having the second height in the second direction greater than the first height.
4 . The GAA FET device of claim 3 , wherein each channel structure of the one or more channel structures, a first extension region of the one or more first extension regions between the channel structure and the first electrode, and a second extension region of the one or more second extension regions between the channel structure and the second electrode are a dumbbell-shaped structure.
5 . The GAA FET device of claim 1 , wherein the fourth height of an inner spacer of the one or more inner spacers tapers as the inner spacer extends away from its adjacent gate structure of the one or more gate structures.
6 . The GAA FET device of claim 1 , wherein the one or more channel structures each comprise a nanowire.
7 . The GAA FET device of claim 1 , wherein the one or more channel structures each comprise a nanoslab.
8 . The GAA FET device of claim 1 , wherein the channel comprises a plurality of channel structures stacked within the first width.
9 . The GAA FET device of claim 1 , wherein the first electrode comprises a source region and the second electrode comprises a drain region.
10 . The GAA FET device of claim 1 , wherein the first electrode comprises a drain region and the second electrode comprises a source region.
11 . The GAA FET device of claim 1 , wherein the channel comprises an N-type semiconductor material (N-type) channel.
12 . The GAA FET device of claim 11 , wherein the channel structure is under a tensile strain.
13 . The GAA FET device of claim 1 , wherein the channel comprises a P-type semiconductor material (P-type) channel.
14 . The GAA FET device of claim 13 , wherein the channel structure is under a compressive strain.
15 . The GAA FET device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
16 . A method of fabricating a gate-all-around (GAA) field effect transistor (FET) device, comprising: forming a first electrode on a substrate; forming a second electrode on the substrate; forming a channel extending in a first direction between the first electrode and the second electrode, the channel having a first width in the first direction, the channel comprising one or more channel structures each having a first height in a second direction orthogonal to the first direction; forming a gate surrounding the channel, wherein the gate comprises one or more gate structures each having a third height in the second direction and each disposed adjacent to at least one channel structure of the one or more channel structures in the second direction; forming one or more inner spacers each adjacent to a gate structure of the one or more gate structures and each having a fourth height directly adjacent to the gate structure that is less than the third height; and forming one or more first extension regions each extending from a channel structure of the one or more channel structures to the first electrode; and the one or more first extension regions each comprising one or more first enhanced extension portions each having a second height in the second direction greater than the first height.
17 . The method of claim 16 , wherein: forming the channel comprises: forming one or more semiconductor material layers each having the second height in the second direction; etching at least a portion of the one or more semiconductor material layers to the first height to form the one or more channel structures each having the first height; and wherein the one or more extension regions comprise end portions of the one or more semiconductor layers having the second height in the second direction.
18 . The method of claim 17 , wherein a ratio of the second height to the first height is greater than 1.4.
19 . The method of claim 17 , wherein the first height is five (5) nanometers (nm) and the second height is eight (8) nm.
20 . The method of claim 16 , wherein forming the channel comprises: forming a plurality of semiconductor material layers each of the first height in the second direction; and forming a plurality of sacrificial layers interleaved with the plurality of semiconductor material layers each of a third height less than the first height in the second direction.

Description

BACKGROUND I. Field of the Disclosure The technology of the disclosure relates generally to field-effect transistors (FET), and more particularly to gate-all-around (GAA) FET. II. Background Transistors are essential components in modern electronic devices. Large numbers of transistors are employed in integrated circuits (ICs) in many modern electronic devices. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices. As electronic devices become more complex in functionality, so does the need to include a greater number of transistors in such devices. However, these electronic devices are also required to have ever greater performance and efficiency. This increase in the number of transistors is achieved in part through continued efforts to miniaturize transistors in ICs (i.e., placing increasingly more transistors into the same amount of space). As a result, gate lengths are also reduced in a scalable fashion, thereby reducing channel length of the transistors. For example, as the channel length in planar transistors is reduced such that the channel length is of the same order of magnitude as depletion layer widths, short channel effects (SCEs) can occur that degrade performance. More specifically. SCEs in planar transistors cause increased current leakage, reduced threshold voltage, and/or threshold voltage roll-off (i.e., reduced threshold voltage at shorter gate lengths), and therefore, reduced gate control. In this regard, alternative FET designs to planar FETs have been developed. These alternative transistor designs provide for a gate material to wrap around at least a portion of a channel structure to provide better gate control over an active channel therein. Better gate control provides reduced current leakage and increased threshold voltage compared to a planar FET of a similar footprint. One example of a gate around FET is a FinFET. A FinFET provides a channel structure formed by a thin semiconductor material “fin” disposed above the substrate between a source and a drain. The FinFET also includes a “wrap-around” gate that wraps around top and side portions of the fin to provide gate control of the channel formed by the channel structure. However, it has become difficult to scale down of the size of FinFETs due to fabrication and performance limitations. In this regard, gate-all-around (GAA) FETs have been further developed. A GAA FET includes one or more nano channel structures of semiconductor material (e.g., nanowires or nanosheets) that are stacked in relationship to each other and disposed between a source and a drain. Each nano channel structure forms part of the channel of the GAA FET. To provide better gate control of the channel, a gate material is disposed all around each of the channel structures as well as between adjacent channel structures. This provides an even greater gate area in the GAA FET to provide reduced current leakage and increased threshold voltage as compared to a planar FET and/or FinFET. SUMMARY OF THE DISCLOSURE Aspects of the present disclosure include an enhanced-shaped extension region for gate-all-around (GAA) field-effect transistor (FET) devices. Related fabrication methods are also disclosed. The GAA FET device includes first and second electrodes disposed on a substrate that provide an electrical path and comprise source/drain regions. The GAA FET device also includes a channel disposed between the first and second electrodes (source or drain). The channel includes one or more channel structure(s) in a stacked arrangement and a gate surrounding the channel structure(s). The channel structure(s) extends in a first direction between the first and second electrodes. The GAA FET device also includes an extension region of semiconductor material coupled from the respective channel to the first and second electrodes to facilitate forming a conductive channel between the source and the drain regions when the GAA FET device is activated. Thus, the area of the extension region between the first and second electrodes and the channel of the GAA FET device forms a series resistance path between the first and second electrodes and the channel. To reduce the parasitic resistance of the channel, the extension region of the GAA FET device has an enhanced extension portion that has an extended height orthogonal to the channel direction. In this manner, the extension region with its enhanced extension portion has a reduced resistance as compared to an extension region not containing the enhanced extension portion, thus reducing the parasitic resistance of the GAA FET device for improved device performance. For example, the increased size of the extension region reduces resistivity by providing a broader carrier pathway between the source and drain regions and the channel of the GAA FET. In another exemplary aspect, the enhanced extension portions of the extension regio