US-12628385-B2 - Semiconductor device and methods of formation

Abstract

A high voltage transistor may include a stepped dielectric layer between a field plate structure and a channel region of the high voltage transistor in a substrate. The stepped dielectric layer may increase the breakdown voltage of the high voltage transistor by reducing the electric field strength near the drain region of the high voltage transistor. In particular, a portion of the stepped dielectric layer near the drain region includes a thickness that is greater relative to a thickness of another portion of the stepped dielectric layer near the gate structure. The increased thickness near the drain region provides increased electric field suppression near the drain region (which operates at high voltages). In this way, the stepped dielectric layer enables the high voltage transistor described herein to achieve higher breakdown voltages without increasing the distance between the gate structure and the drain region of a high voltage transistor.

Inventors

• Kaochao Chen
• Chia-Cheng Ho
• Chia-Jui LEE
• Chia-Yu WEI

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20230417

Claims (20)

1. 1 . A method, comprising: forming a gate structure over a substrate of a semiconductor device; forming a first source/drain region in the substrate, wherein the first source/drain region is on a first side of the gate structure; forming a second source/drain region in the substrate, wherein the second source/drain region is on a second side of the gate structure opposing the first side; forming a dielectric layer over the substrate between the gate structure and the second source/drain region; forming a masking layer over a portion of the dielectric layer; etching the dielectric layer based on the masking layer, wherein the masking layer protects the portion of the dielectric layer from being etched, and wherein etching the dielectric layer based on the masking layer results in the portion of the dielectric layer being a raised portion that is located between non-raised portions of the dielectric layer; removing the masking layer after etching the dielectric layer based on the masking layer; and forming a field plate layer that extends along the dielectric layer after removing the masking layer.
2. 2 . The method of claim 1 , further comprising: forming a blocking layer on the substrate between the gate structure and the second source/drain region, wherein forming the dielectric layer comprises: forming the dielectric layer on the blocking layer.
3. 3 . The method of claim 2 , wherein forming the dielectric layer comprises: forming a stair stepped portion of the dielectric layer on the substrate adjacent to an end of the blocking layer.
4. 4 . The method of claim 2 , wherein forming the dielectric layer comprises: forming a stair stepped portion of the dielectric layer on the second source/drain region adjacent to an end of the blocking layer.
5. 5 . The method of claim 4 , wherein forming the dielectric layer comprises: forming the dielectric layer such that a thickness of the raised portion is included in a range of approximately 10 nanometers to approximately 1000 nanometers.
6. 6 . The method of claim 5 , wherein etching the dielectric layer comprises: etching the dielectric layer such that a thickness of the non-raised portions are included in a range of approximately 10 nanometers to approximately 700 nanometers.
7. 7 . The method of claim 1 , wherein forming the dielectric layer comprises: forming the dielectric layer over the gate structure and over the first source/drain region.
8. 8 . A method of forming a semiconductor device, comprising: forming a first source/drain region in a substrate; forming a second source/drain region in the substrate; forming a gate structure over the substrate and between the first source/drain region and the second source/drain region; forming a dielectric layer over the substrate and between the gate structure and the second source/drain region, wherein the dielectric layer comprises a raised portion and a plurality of non-raised portions adjacent to the raised portion, wherein a thickness of the raised portion is greater than a thickness of the non-raised portions; and forming a field plate layer that extends along the dielectric layer, wherein a shape of the field plate layer conforms to a profile of the dielectric layer.
9. 9 . The method of claim 8 , wherein the semiconductor device comprises a high voltage lateral diffused metal oxide semiconductor (LDMOS) transistor; and wherein the dielectric layer is over a portion of a channel region of the LDMOS transistor between the gate structure and the second source/drain region.
10. 10 . The method of claim 8 , wherein the dielectric layer further comprises: an angled portion that extends along a sidewall of the gate structure, wherein the angled portion is connected to one of the non-raised portions, and wherein the one of the non-raised portions is approximately parallel with the substrate.
11. 11 . The method of claim 10 , wherein a width of the one of the non-raised portions is included in a range of approximately 50 nanometers to approximately 5000 nanometers.
12. 12 . The method of claim 10 , wherein a thickness of the one of the non-raised portions is included in a range of approximately 10 nanometers to approximately 700 nanometers.
13. 13 . The method of claim 10 , wherein the field plate layer comprises: an angled portion on the angled portion of the dielectric layer; a non-raised portion on the one of the non-raised portions of the dielectric layer; and a raised portion on the raised portion of the dielectric layer; and a contact over the raised portion of the field plate layer.
14. 14 . The method of claim 8 , wherein a thickness of the raised portion is included in a range of approximately 10 nanometers to approximately 1000 nanometers.
15. 15 . A method of forming a semiconductor device, comprising: forming a first source/drain region in a substrate; forming a second source/drain region in the substrate; forming a gate structure over the substrate and between the first source/drain region and the second source/drain region; forming a dielectric layer over the substrate and between the gate structure and the second source/drain region, wherein the dielectric layer comprises: an angled portion over a sidewall of the gate structure; a non-raised portion connected to the angled portion and approximately parallel with the substrate; a raised portion connected to the non-raised portion at a first side of the raised portion, wherein the raised portion has a top surface that is at a height in the semiconductor device that is greater relative to a height of a top surface of the non-raised portion; and a stair stepped portion connected to the raised portion at a second side of the raised portion opposing the first side; and forming a field plate layer that extends along the angled portion, the non-raised portion, and a portion of the raised portion of the dielectric layer, wherein a top surface of a raised portion of the field plate layer is higher than a top surface of a non-raised portion of the field plate layer.
16. 16 . The method of claim 15 , wherein forming the stair stepped portion comprises: forming a first stepped portion having a top surface that is approximately co-planar with the top surface of the non-raised portion; and forming a second stepped portion having a top surface that is at a height in the semiconductor device that is less than a height of the top surface of the first stepped portion.
17. 17 . The method of claim 16 , further comprising: forming a contact over the raised portion of the field plate layer.
18. 18 . The method of claim 16 , wherein the raised portion of the field plate layer is over the raised portion of the dielectric layer.
19. 19 . The method of claim 15 , further comprising: forming a blocking layer on the substrate between the gate structure and the second source/drain region, wherein the dielectric layer is included on the blocking layer.
20. 20 . The method of claim 19 , wherein the stair stepped region comprises: a first stepped portion on the blocking layer; and a second stepped portion adjacent to the blocking layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This Patent Applications claims priority to U.S. Provisional Patent Application No. 63/381,679, filed on Oct. 31, 2022, and entitled “SEMICONDUCTOR DEVICE AND METHODS OF FORMATION.” The disclosure of the prior Application is considered part of and is incorporated by reference into this Patent Application. BACKGROUND A high voltage transistor is a type of metal oxide semiconductor (MOS) transistor may be configured to operate at a higher drain voltage relative to a low voltage transistor. Low voltage transistors may be used in applications such as logic circuits (e.g., processors), memory (e.g., static random access memory (SRAM), and/or input/output (I/O) circuits, among other examples. High voltage transistors may be used in applications such as integrated circuit (IC) drivers, power ICs, image sensors, power management, display driver ICs (DDICs), bipolar complementary metal oxide semiconductor (CMOS) diffused metal oxide semiconductor (DMOS) ICs (BCD ICs), and/or image signal processing (ISP) ICs, among other examples. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a diagram of an example environment in which systems and/or methods described herein may be implemented. FIG. 2 is a diagram of a portion of an example device described herein. FIG. 3 is a diagram of an example semiconductor device described herein. FIGS. 4A and 4B are diagrams of an example implementation of a semiconductor device described herein. FIGS. 5A-5C are diagrams of an example implementation of a semiconductor device described herein. FIGS. 6A-6C are diagrams of an example implementation of electric field distributions described herein. FIGS. 7A-7L are diagrams of an example implementation of forming a semiconductor device described herein. FIG. 8 is a diagram of example components of a device described herein. FIG. 9 is a flowchart of an example process associated with forming a semiconductor device described herein. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. To operate at higher drain voltages, a high voltage transistor may be manufactured to withstand a high breakdown voltage. Breakdown voltage is a voltage at or near which a transistor ceases to operate according to the intended operating principles of the transistor. In a high voltage transistor, gate-to-drain voltages may sometimes satisfy or exceed the breakdown voltage of the high voltage transistor due to the high grain voltages experienced by the high voltage transistor. In some cases, a distance between a gate structure and a drain region of a high voltage transistor may be increased to increase the breakdown voltage (BV) of the high voltage transistor. However, increasing the distance between the gate structure and the drain region increases the footprint of the high voltage transistor. The increased footprint may reduce the operating efficiency of the high voltage transistor, may increase resistance in the high voltage transistor, and/or may result in reduced density of high voltage transistors in a semiconductor device, among other