US-12628386-B2 - Semiconductor device and manufacturing method of semiconductor device

US12628386B2US 12628386 B2US12628386 B2US 12628386B2US-12628386-B2

Abstract

Provided is a semiconductor device including a transistor portion, in which the transistor portion has a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an accumulation region of the first conductivity type provided above the drift region, a plurality of trench portions provided to extend from a front surface of the semiconductor substrate to the drift region, and a trench bottom portion of the second conductivity type provided in bottom portions of the plurality of trench portions, and the accumulation region has a doping concentration with a half width of 0.3 μm or more.

Inventors

Nao SUGANUMA
Yosuke Sakurai
Seiji Noguchi
Ryutaro Hamasaki
Takuya Yamada

Assignees

FUJI ELECTRIC CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230724
Priority Date: 20220831

Claims (10)

1 . A semiconductor device comprising a transistor portion, wherein the transistor portion has: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an accumulation region of the first conductivity type provided above the drift region; a plurality of trench portions provided to extend from a front surface of the semiconductor substrate to the drift region; and a trench bottom portion of the second conductivity type provided in bottom portions of the plurality of trench portions, and the accumulation region has a doping concentration with a half width of 0.3 μm or more.
2 . The semiconductor device according to claim 1 , wherein the accumulation region has a doping concentration with a half width of 0.3 μm or more, from a peak position of the doping concentration to a back surface side of the semiconductor substrate, in a depth direction of the semiconductor substrate.
3 . The semiconductor device according to claim 1 , wherein a thickness of the accumulation region is 2.5 μm or more and 4.0 μm or less.
4 . The semiconductor device according to claim 1 , wherein a peak doping concentration of the accumulation region is 1.8E16 cm −3 or more and 1.9E17 cm −3 or less.
5 . The semiconductor device according to claim 1 , wherein the accumulation region is provided, in a trench array direction, to extend from a side wall of a first trench portion of the plurality of trench portions to a side wall of a second trench portion that is adjacent.
6 . The semiconductor device according to claim 1 , wherein a lower end of the accumulation region is in contact with the trench bottom portion.
7 . The semiconductor device according to claim 1 , wherein a lower end of the accumulation region is spaced apart from the trench bottom portion.
8 . The semiconductor device according to claim 1 , wherein the accumulation region has a first accumulation region, and a second accumulation region separated from the first accumulation region by the base region.
9 . The semiconductor device according to claim 1 , wherein the transistor portion has, in a top view, an electron passing region in which the trench bottom portion is not provided, and the accumulation region is not provided in the electron passing region.
10 . The semiconductor device according to claim 9 , comprising: an active portion that has the transistor portion; and an edge termination structure portion provided at an outer circumference of the active portion, wherein a well region of the second conductivity type is provided in the semiconductor substrate, from at least a part of the active portion to the edge termination structure portion, and the trench bottom portion has, in the top view, a first trench bottom portion that is provided in a center portion side of the active portion relative to the electron passing region and that is electrically floating, and a second trench bottom portion that is provided in an edge termination structure portion side relative to the electron passing region and that is in contact with the well region.

Description

The contents of the following patent application(s) are incorporated herein by reference: NO. 2022-138195 filed in JP on Aug. 31, 2022 BACKGROUND 1. Technical Field The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device. 2. Related Art Patent Document 1 discloses an IGBT provided with a second portion 172 of an n+ type having an impurity concentration higher than a first portion 171 of an n− type. Patent Document 2 discloses an insulated gate semiconductor device provided with an N layer 43 having an impurity concentration higher than an N− layer 42 between the N− layer 42 and a P base layer 44. PRIOR ART DOCUMENT Patent Document Patent Document 1: Specification of U.S. Pat. No. 9,653,568Patent Document 2: Japanese Patent Application Publication No. H08-316479 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a figure showing an example of an upper surface of a semiconductor device 100 according to an example embodiment. FIG. 2A is a figure showing an example of a cross section a-a′ in FIG. 1. FIG. 2B is an enlarged drawing of a region A in FIG. 2A. FIG. 3 is a figure showing another example of the cross section a-a′ in FIG. 1. FIG. 4 is a figure showing another example of the cross section a-a′ in FIG. 1. FIG. 5 is a figure showing a relationship between a dose amount and an electric field intensity in an accumulation region of a semiconductor device according to a comparison example. FIG. 6 is a figure showing a relationship between a dose amount and an electric field intensity in an accumulation region 16 of the semiconductor device 100 according to an example embodiment. FIG. 7A is a figure showing an example of a manufacturing method of the semiconductor device 100 according to an example embodiment. FIG. 7B is a figure showing an example of the manufacturing method of the semiconductor device 100 according to an example embodiment. FIG. 8 is a figure showing a relationship between the dose amount and a doping concentration in the accumulation region and a trench bottom portion of the semiconductor device according to an example embodiment and a comparison example. DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the present invention will be described. However, the following embodiments are not for limiting the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are essential to the solution of the invention. In the present specification, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as ‘upper’ or ‘front’ and the other side is referred to as ‘lower’ or ‘back’. One surface of two principal surfaces of a substrate, a layer, or another member is referred to as a front surface, and the other surface is referred to as a back surface. “Upper” and “lower” directions are not limited to a direction of gravity, or a direction in which a semiconductor device is mounted. As used herein, technical matters may be described with orthogonal coordinate axes consisting of an X axis, a Y axis, and a Z axis. The orthogonal coordinate axes are merely for specifying relative positions of components, and are thus not for limiting to a specific direction. For example, the Z axis is not limited to representing a height direction with respect to the ground. Note that a +Z axis direction and a −Z axis direction are directions opposite to each other. When a direction is referred to as a “Z axis direction” without these “+” and “−” signs, it means the Z axis direction is parallel to +Z and −Z axes. In the present specification, orthogonal axes parallel to the front surface and the back surface of the semiconductor substrate are referred to as the X axis and the Y axis. In addition, an axis perpendicular to the front surface and the back surface of the semiconductor substrate is referred to as the Z axis. As used herein, a direction of the Z axis may be referred to as a depth direction. In addition, in the present specification, a direction parallel to the front surface and the back surface of the semiconductor substrate, including the X axis and the Y axis, may be referred to as a horizontal direction. As used herein, phrases such as “same” or “equal” may be used even when there is an error caused due to a variation in a manufacturing step or the like. This error is within a range of 10% or less, for example. In the present specification, a conductivity type of a doping region where doping has been carried out with an impurity is described as a P type or an N type. In the present specification, the impurity may particularly mean either a donor of the N type or an acceptor of the P type, and may be described as a dopant. In the present specification, doping means introducing the donor or the acceptor into the semiconductor substrate and turning it into a semiconductor showing the conductivity type of the N type, or a semiconductor showing the conductivi