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US-12628387-B2 - Semiconductor device and method for fabricating the same

US12628387B2US 12628387 B2US12628387 B2US 12628387B2US-12628387-B2

Abstract

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.

Inventors

  • Chin-Hung Chen
  • Ssu-I Fu
  • YU-HSIANG LIN
  • Po-Kuang Hsieh
  • Jia-He Lin
  • Sheng-Yao HUANG

Assignees

  • UNITED MICROELECTRONICS CORP.

Dates

Publication Date
20260512
Application Date
20230512
Priority Date
20230411

Claims (20)

  1. 1 . A method for fabricating a semiconductor device, comprising: providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region; forming a first trench on the HV region; forming a second trench adjacent to the first trench and extending the first trench to form a third trench; forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, wherein a bottom surface of the second STI is lower than a bottom surface of the first STI; and forming a first gate structure and source/drain regions on the HV region, wherein the first gate structure is disposed between the first STI and the second STI, and the first STI and the second STI are disposed between the first gate structure and the source/drain regions, respectively.
  2. 2 . The method of claim 1 , further comprising: forming the first trench on the HV region and a fourth trench on the MV region; forming the second trench, the third trench, and extending the fourth trench to form a fifth trench and a sixth trench; forming a dielectric layer in the second trench, the third trench, the fifth trench, and the sixth trench; planarizing the dielectric layer to form the first STI, the second STI, a third STI in the fifth trench, and a fourth STI in the sixth trench; forming a first gate dielectric layer between the first STI and the second STI; forming a second gate dielectric layer between the third STI and the fourth STI; forming the first gate structure on the first gate dielectric layer; and forming a second gate structure on the second gate dielectric layer.
  3. 3 . The method of claim 2 , wherein top surfaces of the first STI and the third STI are coplanar.
  4. 4 . The method of claim 2 , wherein the third STI comprises a left portion and a right portion and a bottom surface of the right portion is lower than a bottom surface of the left portion.
  5. 5 . The method of claim 4 , wherein the bottom surface of the right portion of the third STI is even with the bottom surface of the second STI.
  6. 6 . The method of claim 4 , wherein the fourth STI comprises a left portion and a right portion and a bottom surface of the left portion is lower than a bottom surface of the right portion.
  7. 7 . The method of claim 6 , wherein the bottom surface of the left portion of the fourth STI is even with the bottom surface of the second STI.
  8. 8 . The method of claim 6 , wherein the bottom surface of the right portion of the third STI is even with the bottom surface of the left portion of the fourth STI.
  9. 9 . A semiconductor device, comprising: a substrate having a high-voltage (HV) region and a medium-voltage (MV) region; a first shallow trench isolation (STI) and a second STI in the substrate of the HV region, wherein a bottom surface of the second STI is lower than a bottom surface of the first STI; and a first gate structure and source/drain regions on the HV region, wherein the first gate structure is disposed between the first STI and the second STI, and the first STI and the second STI are disposed between the first gate structure and the source/drain regions, respectively.
  10. 10 . The semiconductor device of claim 9 , further comprising: a third STI and a fourth STI in the substrate of the MV region; a first gate dielectric layer between the first STI and the second STI; a second gate dielectric layer between the third STI and the fourth STI; the first gate structure on the first gate dielectric layer; and a second gate structure on the second gate dielectric layer.
  11. 11 . The semiconductor device of claim 10 , wherein top surfaces of the first STI and the third STI are coplanar.
  12. 12 . The semiconductor device of claim 10 , wherein the third STI comprises a left portion and a right portion and a bottom surface of the right portion is lower than a bottom surface of the left portion.
  13. 13 . The semiconductor device of claim 12 , wherein the bottom surface of the right portion of the third STI is even with the bottom surface of the second STI.
  14. 14 . The semiconductor device of claim 12 , wherein the fourth STI comprises a left portion and a right portion and a bottom surface of the left portion is lower than a bottom surface of the right portion.
  15. 15 . The semiconductor device of claim 14 , wherein the bottom surface of the left portion of the fourth STI is even with the bottom surface of the second STI.
  16. 16 . The semiconductor device of claim 14 , wherein the bottom surface of the right portion of the third STI is even with the bottom surface of the left portion of the fourth STI.
  17. 17 . A semiconductor device, comprising: a substrate having a high-voltage (HV) region and a medium-voltage (MV) region; a first shallow trench isolation (STI) and a second STI in the substrate of the MV region; and a first gate dielectric layer between the first STI and the second STI, wherein the first gate dielectric layer has a concave-shaped top surface.
  18. 18 . The semiconductor device of claim 17 , wherein the first gate dielectric layer has a first thickness at a center thereof and a second thickness at a first sidewall thereof, and the first thickness is less than the second thickness.
  19. 19 . The semiconductor device of claim 18 , wherein the first gate dielectric layer has a third thickness at a second sidewall opposite to the first sidewall relative to the center, and the first thickness is less than the third thickness.
  20. 20 . The semiconductor device of claim 19 , wherein the second thickness is equal to the third thickness.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a method of fabricating semiconductor device, and more particularly to a method of integrating high-voltage (HV) device, medium-voltage (MV) device, and low-voltage (LV) device. 2. Description of the Prior Art In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffusion MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance. Moreover with the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate. However as the scale of current devices continue to decrease the integration of high-voltage devices and FinFET devices start to face numerous challenges such as current leakage and control of breakdown voltage. Hence, how to improve the current fabrication for improving performance of the device has become an important task in this field. SUMMARY OF THE INVENTION According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI. According to another aspect of the present invention, a semiconductor device includes a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, a first shallow trench isolation (STI) and a second STI in the substrate of the HV region, and a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI. According to yet another aspect of the present invention, a semiconductor device includes a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, a first shallow trench isolation (STI) and a second STI in the substrate of the MV region, and a first gate dielectric layer between the first STI and the second STI. Preferably, a first thickness closer to a center of the first gate dielectric layer and a second thickness closer to a first side of the first gate dielectric layer are different. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-11 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. FIGS. 9-14 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION Referring to FIGS. 1-8, FIGS. 1-8 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention, in which FIG. 1 illustrates a top view for fabricating the semiconductor device according to an embodiment of the present invention and FIGS. 2-11 illustrate cross-section views for fabricating the semiconductor device along the sectional lines AA′, BB′, and CC′. As shown in FIGS. 1-2, a substrate 12 such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided and three or more transistor regions including a high voltage (HV) region 14, a medium-voltage (MV) region 16, and a low-voltage (LV) region 18 are defined on the substrate 12, in which at least a HV device 114 is disposed on