US-12628389-B2 - Nanosheet FET with controlled overlay mark

Abstract

A semiconductor device includes a nanosheet field effect transistor (FET), and an overlay mark adjacent to the nanosheet FET. The overlay mark includes a middle section, a first vertical spacer segment adjacent to a first end of the overlay mark, and a second vertical spacer segment adjacent to a second end of the overlay mark. The first vertical spacer segment and the second vertical spacer segment are isolated from direct contact with the middle section by a shallow trench isolation (STI).

Inventors

• Min Gyu Sung
• Susan Ng Emans
• Tao Li
• Ruilong Xie
• Anton Tokranov

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20231207

Claims (20)

1. 1 . A semiconductor device comprising: a nanosheet field effect transistor (FET); and an overlay mark adjacent to the nanosheet FET, wherein the overlay mark comprises: a middle section; a first vertical spacer segment adjacent to a first end of the overlay mark; and a second vertical spacer segment adjacent to a second end of the overlay mark, wherein the first vertical spacer segment and the second vertical spacer segment are isolated form direct contact with the middle section by a shallow trench isolation (STI).
2. 2 . The semiconductor device of claim 1 , further comprising: first alternating layers of a first material and a second material, the first alternating layers extending vertically on the first end of the middle section; and second alternating layers of the first material and a third material, the second alternating layers extending vertically on the second end of the middle section.
3. 3 . The semiconductor device of claim 2 , wherein: the first material includes silicon, the second material includes the first vertical spacer segment, and the third material includes the second vertical spacer segment.
4. 4 . The semiconductor device of claim 2 , wherein the middle section further comprises: a substrate horizontally extended from the first end to the second end; and a source/drain region horizontally extended over the substrate, wherein portions of the source/drain region on the first end and the second end are extended vertically and are in contact with the first alternating layers and the second alternating layers.
5. 5 . The semiconductor device of claim 2 , wherein: the first alternating layers are isolated from the first vertical spacer segment via the STI; and the second alternating layers are isolated from the second vertical spacer segment via the STI.
6. 6 . The semiconductor device of claim 4 , wherein the source/drain region comprises silicon or silicon germanium.
7. 7 . The semiconductor device of claim 1 , wherein the nanosheet FET includes nanosheets of silicon layers and silicon germanium layers.
8. 8 . A semiconductor device, the semiconductor device comprising: a nanosheet field effect transistor (FET); and an overlay mark adjacent to the nanosheet FET, wherein the overlay mark comprises: a middle section; a first spacer segment vertically extended over sidewalls of the middle section on a first end; and a second spacer segment vertically extended over sidewalls of the middle section on a second end.
9. 9 . The semiconductor device of claim 8 , wherein the middle section further comprises: a substrate horizontally extended from the first end to the second end; and a source/drain region horizontally extended over the substrate.
10. 10 . The semiconductor device of claim 9 , wherein the source/drain region comprises silicon or silicon germanium.
11. 11 . The semiconductor device of claim 8 , wherein the nanosheet FET includes nanosheets of silicon layers and silicon germanium layers.
12. 12 . A method of fabrication of a semiconductor device comprising: forming a nanosheet field effect transistor (FET); and forming an overlay mark adjacent to the nanosheet FET, wherein forming the overlay mark comprises: forming a middle section; forming a first vertical spacer segment adjacent to a first end of the overlay mark; and forming a second vertical spacer segment adjacent to a second end of the overlay mark; and isolating the first vertical spacer segment and the second vertical spacer segment from the middle section by a shallow trench isolation (STI).
13. 13 . The method of claim 12 , wherein forming the overlay mark further comprises: forming a substrate extended between the first end and the second end; and forming a source/drain region over the substrate.
14. 14 . The method of claim 13 , further comprising: forming the STI over sidewalls of the middle section on the first end and the second end; removing an isolation layer from a top surface of the substrate; and forming a spacer layer over the top surface of the substrate.
15. 15 . The method of claim 14 , further comprising: forming first alternating layers of a first material and a second material over the sidewalls of the middle section on the first end; and forming second alternating layers of the first material and a third material over the sidewalls of the middle section on the second end.
16. 16 . The method of claim 15 , wherein: the first material includes silicon, the second material includes the first vertical spacer segment, and the third material includes the second vertical spacer segment.
17. 17 . The method of claim 13 , wherein forming the source/drain region further comprises extending the source/drain region vertically over sidewalls of the first end and sidewalls of the second end.
18. 18 . The method of claim 15 , further comprising: isolating the first alternating layers from the first vertical spacer segment via the STI; and isolating the second alternating layers from the second vertical spacer segment via the STI.
19. 19 . The method of claim 13 , wherein the source/drain region comprises silicon or silicon germanium.
20. 20 . The method of claim 12 , wherein forming the nanosheet FET further includes forming nanosheets of silicon layers and silicon germanium layers.

Description

BACKGROUND Technical Field The present disclosure generally relates to transistors, and more particularly, to nanosheet transistors with controlled overlay mark and methods of creation thereof. Description of the Related Art Overlay marks and overlay metrology enable precise alignment and error correction between device layers during multi-step semiconductor manufacturing. These overlay marks can be used to match the electrical connections across integrated device structures. SUMMARY According to an embodiment, a semiconductor device includes a nanosheet field effect transistor (FET), and an overlay mark adjacent to the nanosheet FET. The overlay mark includes a middle section, a first vertical spacer segment adjacent to a first end of the overlay mark, and a second vertical spacer segment adjacent to a second end of the overlay mark. The first vertical spacer segment and the second vertical spacer segment are isolated form direct contact with the middle section by a shallow trench isolation (STI). In on embodiment, the semiconductor device includes first alternating layers extended vertically on the first end of the middle section, and second alternating layers extended vertically on the second end of the middle section. In one embodiment, the first alternating layers include silicon and the first vertical spacer segment, and the second alternating layers include silicon and the second vertical spacer segment. In one embodiment, the middle section further includes a substrate horizontally extended from the first end to the second end, and a source/drain region horizontally extended over the substrate. Portions of the source/drain region on the first end and the second end are extended vertically and are in contact with the first alternating layers and the second alternating layers. In one embodiment, the first alternating layers are isolated from the first spacer segment via the STI, and the second alternating layers are isolated from the second spacer segment via the STI. In one embodiment, the source/drain region comprises silicon or silicon germanium. In one embodiment, the nanosheet FET includes nanosheets of silicon layers and silicon germanium layers. According to an embodiment, a semiconductor device includes a nanosheet field effect transistor (FET) and an overlay mark adjacent to the nanosheet FET. The overlay mark includes a middle section, a first spacer segment vertically extended over sidewalls of the middle section on a first end, and a second spacer segment vertically extended over sidewalls of the middle section on a second end. In one embodiment, the middle section further includes a substrate horizontally extended from the first end to the second end, and a source/drain region horizontally extended over the substrate. In one embodiment, the source/drain region includes silicon or silicon germanium. In one embodiment, the nanosheet FET includes nanosheets of silicon layers and silicon germanium layers. According to an embodiment, a method of fabricating a semiconductor device includes forming a nanosheet field effect transistor (FET) and forming an overlay mark adjacent to the nanosheet FET. Forming the overlay mark includes forming a middle section, forming a first vertical spacer segment adjacent to a first end of the overlay mark, and forming a second vertical spacer segment adjacent to a second end of the overlay mark, and isolating the first spacer segment and the second spacer segment from the middle section by a shallow trench isolation (STI). In one embodiment, forming the overlay mark further includes forming a substrate extended between the first end and the second end, and forming a source/drain region over the substrate. In one embodiment, the method includes forming the STI over sidewalls of the middle section on the first end and the second end, removing an isolation layer from a top surface of the substrate, and forming a spacer layer over the top surface of the substrate. In one embodiment, the method includes forming first alternating layers over the sidewalls of the middle section on the first end, and forming second alternating layers over the sidewalls of the middle section on the second end. In one embodiment, the first alternating layers include silicon and the first spacer segment, and the second alternating layers include silicon and the second spacer segment. In one embodiment, forming the source/drain region further includes extending the source/drain region vertically over the sidewalls of the first end and the sidewalls of the second end. In one embodiment, the method includes isolating the first alternating layers from the first spacer segment via the STI. The second alternating layers are isolated from the second spacer segment via the STI. In one embodiment, the source/drain region includes silicon or silicon germanium. In one embodiment, forming the nanosheet FET further includes forming nanosheets of silicon layers and silicon germanium layers. These and ot