US-12628390-B2 - Nanosheet stacks with dielectric isolation layers

Abstract

A semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer.

Inventors

• Juntao Li
• Ruilong Xie
• Julien Frougier
• Nicolas Jean Loubet

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20220920

Claims (20)

1. 1 . A semiconductor structure comprising: a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers; a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers; and a gate dielectric layer (i) disposed over a top surface of the first dielectric isolation layer and (ii) not disposed over at least a portion of a top surface of the second dielectric isolation layer.
2. 2 . The semiconductor structure of claim 1 , wherein the gate dielectric layer is further disposed on a bottom surface and sidewalls of both the first dielectric isolation layer and the second dielectric isolation layer.
3. 3 . The semiconductor structure of claim 1 , wherein the first dielectric isolation layer has a first width that is equal to or greater than widths of the underlying one or more first nanosheet channel layers of the first nanosheet stack, and wherein the second dielectric isolation layer has a second width that is equal to or greater than widths of the underlying one or more second nanosheet channel layers of the second nanosheet stack.
4. 4 . The semiconductor structure of claim 1 , further comprising: a first gate conductor layer surrounding the one or more first nanosheet channel layers of the first nanosheet stack; and a second gate conductor layer surrounding the one or more second nanosheet channel layers of the second nanosheet stack.
5. 5 . The semiconductor structure of claim 4 , wherein the second gate conductor layer further surrounds the first gate conductor layer.
6. 6 . The semiconductor structure of claim 4 , wherein the first gate conductor layer comprises a first work function metal material and the second gate conductor layer comprises a second work function metal material.
7. 7 . The semiconductor structure of claim 1 , further comprising a shallow trench isolation region disposed over a substrate between the first nanosheet stack and the second nanosheet stack.
8. 8 . The semiconductor structure of claim 7 , wherein the gate dielectric layer is further (iii) disposed over a first portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack and (iv) not disposed over a second portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack.
9. 9 . The semiconductor structure of claim 8 , wherein the second portion of the shallow trench isolation region is recessed below a top surface of the first portion of the shallow trench isolation region.
10. 10 . The semiconductor structure of claim 8 , wherein the first portion of the shallow trench isolation region is adjacent the first nanosheet stack and the second portion of the shallow trench isolation region is adjacent the second nanosheet stack.
11. 11 . A semiconductor structure comprising: a first nanosheet stack; a second nanosheet stack; a shallow trench isolation region disposed over a substrate between the first nanosheet stack and the second nanosheet stack; and a gate dielectric layer (i) disposed over a first portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack and (ii) not disposed over a second portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack.
12. 12 . The semiconductor structure of claim 11 , wherein the second portion of the shallow trench isolation region is recessed below a top surface of the first portion of the shallow trench isolation region.
13. 13 . The semiconductor structure of claim 11 , wherein the first portion of the shallow trench isolation region is adjacent the first nanosheet stack and the second portion of the shallow trench isolation region is adjacent the second nanosheet stack.
14. 14 . The semiconductor structure of claim 11 , wherein the first nanosheet stack comprises one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, and wherein the second nanosheet stack comprises one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers.
15. 15 . The semiconductor structure of claim 14 , wherein the gate dielectric layer is further disposed on: a bottom surface and sidewalls of both the first dielectric isolation layer and the second dielectric isolation layer; and a top surface of the first dielectric isolation layer.
16. 16 . An integrated circuit comprising: a nanosheet transistor structure comprising: a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers; a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers; and a gate dielectric layer (i) disposed over a top surface of the first dielectric isolation layer and (ii) not disposed over at least a portion of a top surface of the second dielectric isolation layer.
17. 17 . The integrated circuit of claim 16 , wherein the gate dielectric layer is further disposed on a bottom surface and sidewalls of both the first dielectric isolation layer and the second dielectric isolation layer.
18. 18 . The integrated circuit of claim 16 , wherein the nanosheet transistor structure further comprises a shallow trench isolation region disposed over a substrate between the first nanosheet stack and the second nanosheet stack.
19. 19 . The integrated circuit of claim 18 , wherein the gate dielectric layer is further (iii) disposed over a first portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack and (iv) not disposed over a second portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack.
20. 20 . The integrated circuit of claim 19 , wherein the second portion of the shallow trench isolation region is recessed below a top surface of the first portion of the shallow trench isolation region.

Description

BACKGROUND The present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous within many products, particularly as they continue to decrease in cost and size. There is a continued desire to reduce the size of structural features and/or to provide a greater amount of structural features for a given chip size. Miniaturization, in general, allows for increased performance at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, field-effect transistors (FETs), and capacitors. SUMMARY Embodiments of the invention provide techniques for forming semiconductor structures with dielectric isolation layers on top of stacks of nanosheet channel layers of nanosheet stacks. In one embodiment, a semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer. In another embodiment, a semiconductor structure comprises a first nanosheet stack, a second nanosheet stack, a shallow trench isolation region disposed over a substrate between the first nanosheet stack and the second nanosheet stack, and a gate dielectric layer (i) disposed over a first portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack and (ii) not disposed over a second portion of the shallow trench isolation region between the first nanosheet stack and the second nanosheet stack. In another embodiment, an integrated circuit comprises a nanosheet transistor structure comprising a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer. These and other features and advantages of embodiments described herein will become more apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A depicts a side cross-sectional view of a structure following patterning of an organic planarization layer over portions of a gate conductor layer surrounding a first one of two nanosheet stacks, according to an embodiment of the invention. FIG. 1B depicts a side cross-sectional view of the structure of FIG. 1B following etching of portions of the gate conductor layer surrounding a second one of the two nanosheet stacks, the etching including an over-etch of portions of the gate conductor layer under the organic planarization layer patterned over the first one of the two nanosheet stacks, according to an embodiment of the invention. FIG. 2A shows a first side cross-sectional view of a structure following formation of a nanosheet stack and shallow trench isolation regions over a substrate, according to an embodiment of the invention. FIG. 2B shows a second side cross-sectional view of the structure following formation of the nanosheet stack and the shallow trench isolation regions over the substrate, according to an embodiment of the invention. FIG. 2C shows a top-down view of a structure showing nanosheet stacks and gate regions illustrating where the first and second side cross-sectional views of FIGS. 2A and 2B are taken, according to an embodiment of the invention. FIG. 3A shows a side cross-sectional view of the structure of FIG. 2A following gate patterning and formation of dielectric isolation layers, inner spacers, source/drain regions, and an interlayer dielectric layer, according to an embodiment of the invention. FIG. 3B shows a side cross-sectional view of the structure of FIG. 2B following the gate patterning and the formation of the dielectric isolation layers, the inner spacers, the source/drain regions, and the interlayer dielectric layer, according to an embodiment of the invention. FIG. 4A shows a side cross-sectional view of the structure of FIG. 3A following dummy gate removal and removal of sacrificial layers in the nanosheet stacks, according to an embodiment of the invention. FIG. 4B shows a side cross-sectional view of the structure of FIG. 3B following the dummy gate removal and the removal of sacrificial layers in the nanosheet stacks, according to an embod