US-12628391-B2 - Method for manufacturing semiconductor and semiconductor

US12628391B2US 12628391 B2US12628391 B2US 12628391B2US-12628391-B2

Abstract

A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.

Inventors

Junjie Li
Enxu LIU
Na Zhou
Jianfeng Gao
Junfeng Li
Jun Luo
Wenwu Wang

Assignees

Institute of Microelectronics, Chinese Academy of Sciences

Dates

Publication Date: 20260512
Application Date: 20231205
Priority Date: 20221208

Claims (10)

1 . A method for manufacturing a semiconductor, comprising: providing a substrate, wherein an active region trench is formed on the substrate, and a channel stack of a gate-all-around transistor, a sacrificial layer between the channel stack, a dummy gate on the channel stack, and a spacer on a sidewall of the sacrificial layer and a sidewall of the dummy gate are formed in the active region trench, and wherein the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect during a growth process of the source crystal structure and the drain crystal structure; and filling a gap between the crystal planes with different orientations of the source crystal structure and a gap between the crystal planes with different orientations of the drain crystal structure by using an isotropic metal material, and forming a source of the gate-all-around transistor in the source trench and a drain of the gate-all-around transistor in the drain trench.
2 . The method of claim 1 , wherein the epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench comprises: epitaxially growing the source crystal structure on a bottom wall and a sidewall of the source trench, a surface of the channel stack and a surface of the spacer by using a reduced pressure vapor deposition epitaxial technology, and stopping the epitaxial growth before the crystal planes with different orientations of the source crystal structure intersect during the growth process of the source crystal structure; and epitaxially growing the drain crystal structure on a bottom wall and a sidewall of the drain trench, a surface of the channel stack and a surface of the spacer by using a reduced pressure vapor deposition epitaxial technology, and stopping the epitaxial growth before the crystal planes with different orientations of the drain crystal structure intersect during the growth process of the drain crystal structure.
3 . The method of claim 2 , wherein a material of the source crystal structure comprises silicon or silicon germanium material, and a material of the drain crystal structure comprises silicon or silicon germanium material.
4 . The method of claim 3 , wherein a growth thickness of the source crystal structure is within a range of 1 nm to 20 nm, and a growth thickness of the drain crystal structure is within a range of 1 nm to 20 nm.
5 . The method of claim 2 , further comprising: performing epitaxial growth and in situ doping on a surface of the source crystal structure and a surface of the drain crystal structure, after epitaxially growing the source crystal structure in the source trench and the drain crystal structure in the drain trench.
6 . The method of claim 1 , further comprising: depositing the isotropic metal material by using an atomic layer deposition, so as to fill the gap between the crystal planes with different orientations of the source crystal structure and the gap between the crystal planes with different orientations of the drain crystal structure.
7 . The method of claim 6 , wherein the isotropic metal material comprises cobalt, titanium, tungsten or titanium nitride.
8 . The method of claim 1 , further comprising: after filling the gap between the crystal planes with different orientations of the source crystal structure and the gap between the crystal planes with different orientations of the drain crystal structure, planarizing the isotropic metal material by using a chemical mechanical polishing planarizing process; etching the isotropic metal material to a predetermined depth by using a metal etching-back process; growing a first dielectric layer on a surface of the isotropic metal material, and chemically and mechanically polishing the first dielectric layer until an upper surface of the dummy gate is exposed; removing the sacrificial layer and the dummy gate; and filling a void with a metal gate material to form a gate of the gate-all-around transistor, wherein the void is formed after removing the sacrificial layer and the dummy gate.
9 . The method of claim 8 , further comprising: forming a second dielectric layer on the first dielectric layer; and forming a source lead-out structure, a drain lead-out structure and a gate lead-out structure in the second dielectric layer, wherein the source lead-out structure is electrically connected to the source, the drain lead-out structure is electrically connected to the drain, and the gate lead-out structure is electrically connected to the gate.
10 . A semiconductor manufactured using the method of claim 1 .

Description

CROSS REFERENCE TO RELATED APPLICATION(S) This application claims priority to Chinese Patent Application No. 202211576204.0, filed on Dec. 8, 2022 and entitled “METHOD FOR MANUFACTURING SEMICONDUCTOR AND SEMICONDUCTOR”, the entire content of which is incorporated herein in its entirety by reference. TECHNICAL FIELD The present disclosure relates to a field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor and a semiconductor. BACKGROUND In a process of continuously miniaturizing CMOS (Complementary Metal Oxide Semiconductor) devices according to Moore's Law, mass production of CMOS devices has entered a technical node of 5 to 3 nm. A use of a gate-all-around transistor device may effectively suppress a short-channel effect. In order to control the short-channel effect, an inner spacer formed on a gate is a necessary process module. SUMMARY The present disclosure provides a method for manufacturing a semiconductor and a semiconductor. In an aspect, the present disclosure provides a method for manufacturing a semiconductor, including: providing a substrate, where an active region trench is formed on the substrate, and a channel stack of a gate-all-around transistor, a sacrificial layer between the channel stack, a dummy gate on the channel stack, and a spacer on a sidewall of the sacrificial layer and a sidewall of the dummy gate are formed in the active region trench, and where the active region trench is divided into a source trench and a drain trench by the channel stack;epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect during a growth process of the source crystal structure and the drain crystal structure; andfilling a gap between the crystal planes with different orientations of the source crystal structure and a gap between the crystal planes with different orientations of the drain crystal structure by using an isotropic metal material, and forming a source of the gate-all-around transistor in the source trench and a drain of the gate-all-around transistor in the drain trench. In an embodiment, the epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench includes: epitaxially growing the source crystal structure on a bottom wall and a sidewall of the source trench, a surface of the channel stack and a surface of the spacer by using a reduced pressure vapor deposition epitaxial technology, and stopping the epitaxial growth before the crystal planes with different orientations of the source crystal structure intersect during the growth process of the source crystal structure; and epitaxially growing the drain crystal structure on a bottom wall and a sidewall of the drain trench, a surface of the channel stack and a surface of the spacer by using a reduced pressure vapor deposition epitaxial technology, and stopping the epitaxial growth before the crystal planes with different orientations of the drain crystal structure intersect during the growth process of the drain crystal structure. In an embodiment, a material of the source crystal structure includes silicon or silicon germanium material, and a material of the drain crystal structure includes silicon or silicon germanium material. In an embodiment, a growth thickness of the source crystal structure is within a range of 1 nm to 20 nm, and a growth thickness of the drain crystal structure is within a range of 1 nm to 20 nm. In an embodiment, the method further includes: performing epitaxial growth and in situ doping on a surface of the source crystal structure and a surface of the drain crystal structure, after epitaxially growing the source crystal structure in the source trench and the drain crystal structure in the drain trench. In an embodiment, the method further includes: depositing the isotropic metal material by using an atomic layer deposition, so as to fill the gap between the crystal planes with different orientations of the source crystal structure and the gap between the crystal planes with different orientations of the drain crystal structure. In an embodiment, the isotropic metal material includes cobalt, titanium, tungsten or titanium nitride. In an embodiment, the method further includes: after filling the gap between the crystal planes with different orientations of the source crystal structure and the gap between the crystal planes with different orientations of the drain crystal structure, planarizing the isotropic metal material by using a chemical mechanical polishing planarizing process; etching the isotropic metal material to a predetermined depth by using a metal etching-back process; growing a first dielectric layer on a surface of the isotropic meta