US-12628394-B2 - Silicon carbide semiconductor device and method for manufacturing the same

US12628394B2US 12628394 B2US12628394 B2US 12628394B2US-12628394-B2

Abstract

A silicon carbide semiconductor device includes an n-type drift layer disposed on an n-type silicon carbide substrate; an n-type current spreading layer disposed on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a p-type base region disposed on a top surface of the current spreading layer; a p-type gate-bottom protection region located in the current spreading layer; a p-type base-bottom embedded region located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure disposed in a trench penetrating the base region to reach the gate-bottom protection region, and a lower recombination region disposed in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer.

Inventors

Keishirou KUMADA

Assignees

FUJI ELECTRIC CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20220224
Priority Date: 20210414

Claims (17)

1 . A silicon carbide semiconductor device comprising: a drift layer of a first conductivity type above a silicon carbide substrate of the first conductivity type; a current spreading layer of the first conductivity type on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a base region of a second conductivity type on a top surface of the current spreading layer; a gate-bottom protection region of the second conductivity type located in the current spreading layer; a base-bottom embedded region of the second conductivity type located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure in a trench penetrating the base region to reach the gate-bottom protection region; a lower recombination region in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer; and an upper recombination region on a bottom surface of the base-bottom embedded region so as to be in direct contact with the bottom surface of the base-bottom embedded region without an intervening layer between an upper surface of the upper recombination region and the bottom surface of the base-bottom embedded region, the upper recombination region including crystal defects configured to recombine minority carriers injected from the base region.
2 . The silicon carbide semiconductor device of claim 1 , wherein the upper recombination region has recombination centers provided with hydrogen or helium as the crystal defects and is disposed in an upper portion of the drift layer so as to cover the bottom surface of the base-bottom embedded region and a bottom edge of the base-bottom embedded region.
3 . The silicon carbide semiconductor device of claim 1 , wherein a side surface of the upper recombination region protrudes by a protrusion width toward a side of the gate-bottom protection region, the protrusion width being less than half of a distance between the base-bottom embedded region and the gate-bottom protection region.
4 . The silicon carbide semiconductor device of claim 3 , wherein the upper recombination region has an area density of crystal defects in a range of 5×10 10 cm −2 or more and 2×10 11 cm −2 or less, and a thickness in range of 0.2 μm or more and 0.5 μm or less.
5 . The silicon carbide semiconductor device of claim 1 , wherein the lower recombination region has recombination centers provided with hydrogen or helium as the crystal defects and is selectively below the base-bottom embedded region.
6 . The silicon carbide semiconductor device of claim 1 , wherein the lower recombination region is on an entire bottom surface of the drift layer.
7 . The silicon carbide semiconductor device of claim 1 , further comprising a gate-bottom recombination region covering the bottom surface of the gate-bottom protection region and a bottom edge of the gate-bottom protection region, including crystal defects configured to recombine minority carriers.
8 . The silicon carbide semiconductor device of claim 1 , wherein the upper recombination region extends so as to be entirely in contact with a bottom surface of the base-bottom embedded region that extends from an end of an active area including the insulated-gate electrode structure is disposed to an outer-edge area that is around the active area.
9 . The silicon carbide semiconductor device of claim 1 , wherein the upper recombination region has recombination centers provided with at least one heavy metal selected from titanium, vanadium, chromium, manganese, iron, platinum and gold as the crystal defects, and the upper recombination region is localized at a lower portion of the base-bottom embedded region.
10 . The silicon carbide semiconductor device of claim 1 , further comprising a buffer layer of the first conductivity type on a top surface of the silicon carbide substrate so as to contact a bottom surface of the drift layer, having a higher impurity concentration than the drift layer.
11 . A silicon carbide semiconductor device comprising: a drift layer of a first conductivity type above a silicon carbide substrate of the first conductivity type; a current spreading layer of the first conductivity type on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a base region of a second conductivity type on a top surface of the current spreading layer; a gate-bottom protection region of the second conductivity type located in the current spreading layer; a base-bottom embedded region of the second conductivity type located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure in a trench penetrating the base region to reach the gate-bottom protection region; and a lower recombination region in a lower portion of the drift layer and selectively below the base-bottom embedded region, including crystal defects configured to recombine minority carriers injected into the drift layer, and having recombination centers provided with hydrogen or helium as the crystal defects, wherein a space between the lower recombination region and another lower recombination region adjacent to the lower recombination region is aligned so as to face the gate-bottom protection region, and a width of the space is larger than a width of the gate-bottom protection region, and in a plan view, an end of the lower recombination region is positioned on a side of the gate-bottom protection region between the base-bottom embedded region and the gate-bottom protection region.
12 . The silicon carbide semiconductor device of claim 11 , further comprising: an upper recombination region on a bottom surface of the base-bottom embedded region, and a local current spreading layer of the first conductivity type in an upper portion of the upper recombination region and in contact with the bottom surface of the base-bottom embedded region.
13 . A silicon carbide semiconductor device comprising: a drift layer of a first conductivity type above a silicon carbide substrate of the first conductivity type; a current spreading layer of the first conductivity type on a top surface of the drift layer, having a higher impurity concentration than the drift layer; a base region of a second conductivity type on a top surface of the current spreading layer; a gate-bottom protection region of the second conductivity type located in the current spreading layer; a base-bottom embedded region of the second conductivity type located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; an insulated-gate electrode structure in a trench penetrating the base region to reach the gate-bottom protection region; and a lower recombination region in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer, wherein the lower recombination region has an area density of the crystal defects in a range of 5×10 11 cm −2 or more and 2×10 12 cm −2 or less, and a thickness in range of 0.5 μm or more and 1.0 μm or less.
14 . A method for manufacturing a silicon carbide semiconductor device comprising: forming an element structure in an active area of a silicon carbide substrate of a first conductivity type, the element structure including, a drift layer of the first conductivity type epitaxially grown on the silicon carbide substrate, a current spreading layer of the first conductivity type on a top surface of the drift layer, having a higher impurity concentration than the drift layer, a base region of a second conductivity type on a top surface of the current spreading layer, a gate-bottom protection region of the second conductivity type located in the current spreading layer, a base-bottom embedded region of the second conductivity type located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region, and an insulated-gate electrode structure in a trench penetrating the base region to reach the gate-bottom protection region, polishing a bottom surface of the silicon carbide substrate, after forming the element structure; and selectively implanting hydrogen ions or helium ions into a lower portion of the drift layer from the polished bottom surface of the silicon carbide substrate to selectively form a lower recombination region, which includes crystal defects for recombining minority carriers, in the lower portion of the drift layer; and selectively implanting ions into an upper portion of the drift layer from the polished bottom surface of the silicon carbide substrate to selectively form an upper recombination region on a bottom surface of the base-bottom embedded region so as to be in direct contact with the bottom surface of the base-bottom embedded region without an intervening layer between an upper surface of the upper recombination region and the bottom surface of the base-bottom embedded region, the upper recombination region including crystal defects for recombining minority carriers.
15 . The method of claim 14 , wherein the selectively implanting ions includes, selectively implanting hydrogen ions, helium ions, or ions of a heavy metal.
16 . The method of claim 15 , wherein the upper recombination region is formed so as to cover the bottom surface of the base-bottom embedded region and a bottom edge of the base-bottom embedded region.
17 . The method of claim 14 , wherein the lower recombination region is selectively formed below the base-bottom embedded region.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2021-68560 filed on Apr. 14, 2021, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide (SiC) semiconductor device and a method for manufacturing the same. 2. Description of the Related Art Commercially available silicon carbide (SiC) single-crystal substrates contain a number of dislocations, including basal plane dislocations (BPD). Such dislocations continuously propagate into an epitaxial layer epitaxially grown on the substrate. Therefore, it is known that the semiconductor device fabricated on the epitaxial substrate adversely affects the characteristics of the semiconductor device. In a SiC semiconductor device such as a MOS field effect transistor (FET), a built-in diode having a p-n junction is formed on an epitaxial substrate. The basal plane dislocations cause degradation of the forward characteristics of the built-in diode which operates in a bipolar mode during turn-off state. For example, minority carriers, which are holes in an n-type semiconductor region, generated by flowing forward current during bipolar operation diffuses in the epitaxial substrate. When the minority carriers recombine at the basal plane dislocation to give recombination energy to the basal plane dislocation, the stacking fault may expand in the epitaxial substrate starting from the basal plane dislocation. As the stacking fault expands, the forward voltage increases and the forward resistance increases when the forward current flows through the built-in diode. As described above, when the device characteristics degrade, the loss generated increases with time and the heat divergence also increases, causing a failure of the semiconductor device. The stacking faults expand from the interface between the n-type substrate and the drift layer which is the n-type epitaxial layer. By arranging an n+-type buffer layer having a high impurity concentration between the substrate and the drift layer, the holes injected from the surface electrode side can be recombined in the buffer layer. Since the recombination energy is released in the buffer layer, the expansion of the stacking faults can be prevented. However, in order to maintain the high breakdown voltage, thickness of the buffer layer is required to be about 10 μm, and thus, the manufacturing cost of the epitaxial substrate may increase. JP 2019-102493 A discloses a method in which the recombination centers (lifetime killers) are formed by implanting hydrogen ions (protons) in the vicinity of the interface between the substrate and the n-type boundary layer. In the method disclosed in JP 2019-102493 A, since the recombination centers are introduced on the entire interface between the substrate and the n-type boundary layer, the on-resistance of the MOSFET may increase. WO 2016-039071 A1 proposes a method of decreasing the reverse recovery loss of the built-in diode by implanting protons or helium ions into the interface of p-n junction at the bottom of the base region of the planar MOSFET to provide the recombination centers. In the method disclosed in WO 2016-039071 A1, since the recombination centers are formed at the bottom of the base region, it is difficult to sufficiently decrease the holes injected into the drift layer. SUMMARY OF THE INVENTION An aspect of the present invention inheres in a SiC semiconductor device, including: (a) a drift layer of a first conductivity type disposed above a silicon carbide substrate of the first conductivity type; (b) a current spreading layer of the first conductivity type disposed on a top surface of the drift layer, having a higher impurity concentration than the drift layer; (c) a base region of a second conductivity type disposed on a top surface of the current spreading layer; (d) a gate-bottom protection region of the second conductivity type located in the current spreading layer; (e) a base-bottom embedded region of the second conductivity type located in the current spreading layer, separated from the gate-bottom protection region to be in contact with a bottom surface of the base region; (f) an insulated-gate electrode structure disposed in a trench penetrating the base region to reach the gate-bottom protection region, and (g) a lower recombination region disposed in a lower portion of the drift layer, including crystal defects configured to recombine minority carriers injected into the drift layer. Another aspect of the present invention inheres in a method for manufacturing a SiC semiconductor device, including: (a) forming an element structure in an active area of a silicon carbide substrate of a first conductivity type, the element structure including, a drift layer of the first conductivity type epitaxially grown on the silicon carbide substrate; a curr