US-12628398-B2 - Semiconductor structure and method of manufacturing the same

US12628398B2US 12628398 B2US12628398 B2US 12628398B2US-12628398-B2

Abstract

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed, wherein the substrate includes an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure. An insulating layer covering the metal gate structure is formed. A semiconductive material layer is formed over the epitaxial structure and the insulating layer, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating layer comprises amorphous semiconductive material. The second portion of the semiconductive material layer is removed. A semiconductor structure thereof is also provided.

Inventors

CHANSYUN DAVID YANG
Ding-Kang SHIH

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date: 20260512
Application Date: 20230113

Claims (20)

1 . A method of manufacturing a semiconductor structure, comprising: receiving a substrate, including an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure; forming an insulating structure covering the metal gate structure, comprising: forming a capping layer over the substrate; forming a dielectric layer over the capping layer; and removing a portion of the dielectric layer and a portion of the capping layer over the epitaxial structure; forming a semiconductive material layer over the epitaxial structure and the insulating structure, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating structure comprises amorphous semiconductive material; and removing the second portion of the semiconductive material layer.
2 . The method of claim 1 , further comprising: exposing the semiconductive material layer to radiation prior to the removal of the second portion of the semiconductive material layer, wherein a frequency of the radiation depends on a material of the semiconductive material layer.
3 . The method of claim 1 , further comprising: exposing a processing gas to radiation to exciting the processing gas prior to the removal of the second portion of the semiconductive material layer.
4 . The method of claim 1 , wherein the formation of the insulating structure further comprises: forming a spacer layer surrounding remaining portions of the dielectric layer and the capping layer and a portion of the metal gate structure above the epitaxial structure.
5 . The method of claim 1 , wherein a surficial part of the first portion of the semiconductive material layer is removed concurrently with the removal of the second portion.
6 . The method of claim 1 , further comprising: exposing the first portion of the semiconductive material layer to radiation after the removal of the second portion of the semiconductive material layer, wherein a frequency of the radiation depends on a material of the semiconductive material layer.
7 . The method of claim 1 , further comprising: forming a silicide layer over the first portion of the semiconductive material layer.
8 . The method of claim 1 , further comprising: forming a conductive plug over the first portion of the semiconductive material layer.
9 . The method of claim 2 , wherein the frequency of the radiation is 1.2 to 4.2 gigahertz (GHz).
10 . The method of claim 2 , wherein a temperature of the second portion of the semiconductive material is greater than a temperature of the first portion of the semiconductive material after exposing the semiconductive material layer to radiation.
11 . The method of claim 10 , wherein the temperature of the second portion of the semiconductive material is in a range 400 to 440° C., and the temperature of the first portion is in a range 370 to 400° C.
12 . The method of claim 5 , wherein a removal rate of the second portion of the semiconductive material is substantially greater than a removal rate of the first portion of the semiconductive material.
13 . The method of claim 3 , wherein the processing gas includes hydrogen chloride, chlorine, or a combination thereof.
14 . The method of claim 1 , wherein the first portion of the semiconductive material layer is grown with a chemical doping concentration in a range of 1E21 to 3E21atoms/cm 3 .
15 . The method of claim 1 , wherein a thickness of the first portion of the semiconductive material layer is in a range of 7 to 15 nm.
16 . The method of claim 7 , wherein a thickness of the silicide layer is in a range of 5 to 9 nm.
17 . The method of claim 8 , wherein a top surface of the conductive plug is aligned with a top surface of the insulating structure.
18 . The method of claim 1 , wherein the capping layer covers an entirety of the metal gate structure.
19 . The method of claim 1 , wherein the capping layer includes a dielectric material different from a dielectric material of the dielectric layer.
20 . The method of claim 7 , further comprising forming a conductive plug over the silicide layer.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims the benefit of prior-filed provisional application No. 63/374,904, filed on 8 Sep. 2022. BACKGROUND Transistors typically include semiconductor regions that are used to form source regions and drain regions. Within the transistors, high contact resistances tend to exist between metal contact plugs and the semiconductor regions. To reduce the contact resistance, metal silicides are formed on surfaces of the semiconductor regions to create, for example, silicon regions, germanium regions, and silicon germanium regions. As a result, the contact plugs contact the silicide regions, thus reducing the contact resistances between the semiconductor regions and the contact plugs. However, as the continuing reduction in device size and increasingly complex circuit arrangements continue to make design and fabrication of integrated circuits (ICs) more challenging and costly, the usage of metal silicides cannot by itself increase device performance to a satisfactory degree. Therefore, there is a need to further reduce the contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a flow diagram of a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 2 is a flow diagram of a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 3 is a schematic three-dimensional diagram of a semiconductor structure in accordance with some embodiments of the present disclosure. FIGS. 4 to 13 are schematic cross-sectional diagrams of the semiconductor structure taken along a line A-A′ in FIG. 3 at different stages of manufacture in accordance with some embodiments of the present disclosure. FIG. 14 is a schematic diagram of an apparatus for performing operations in the manufacture of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 15 is a schematic cross-sectional diagram of a semiconductor structure in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. In addition, the term “source/drain region” or “source/drain regions” may refer to a source or a drain, individually or collectively dependent upon the context. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however,