US-12628401-B2 - Gate profile modulation for semiconductor device

US12628401B2US 12628401 B2US12628401 B2US 12628401B2US-12628401-B2

Abstract

A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.

Inventors

Tien-Shun Chang
Kuo-Ju Chen
Sih-Jie Liu
Wei-Fu Wang
Yi-Chao Wang
Li-Ting Wang
Su-Hao LIU
Huicheng Chang
Yee-Chia Yeo

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20220525

Claims (20)

1 . A method for manufacturing a semiconductor device, comprising: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; increasing a dimension of the dummy gate structure by subjecting the dummy gate structure to an ion implantation process so as to modulate the dimension of the dummy gate structure to a desirable dimension; after the dimension of the dummy gate structure is modulated to the desirable dimension, removing the dummy gate structure to form a recess; forming a metal gate and a gate dielectric in the recess, wherein the metal gate is disposed on the gate dielectric; and forming a conductive capping layer in the recess, wherein the conductive capping layer is formed with an upper portion disposed on a top surface of the gate dielectric, and a lower portion extending from the upper portion and in contact with the metal gate, wherein the patterned structure further includes a spacer layer which includes two lateral portions covering two opposite lateral surfaces of the dummy gate structure, and a top portion covering a top surface of the dummy gate structure, the two lateral portions and the top portion of the spacer layer are formed integrally at the same time; and the method further comprises, after the ion implantation process: removing the top portion of the spacer layer to form a pair of spacers, so that the recess is formed between the pair of spacers.
2 . The method according to claim 1 , wherein the ion implantation process is conducted by ion implanting a dopant into the dummy gate structure and the dielectric layer, and a depth of a peak concentration of the dopant implanted into the dielectric layer is increased by increasing an implant energy at which the ion implantation process is conducted.
3 . The method according to claim 2 , wherein after the ion implantation process, a minimum of the dimension of the dummy gate structure is located at a level equal to the depth of the peak concentration of the dopant implanted into the dielectric layer.
4 . The method according to claim 1 , wherein the ion implantation process is conducted at a temperature in a range from −200° C. to 500° C.
5 . The method according to claim 1 , wherein the ion implantation process is conducted at an implant energy in a range from 1 keV to 30 keV.
6 . The method according to claim 1 , wherein the ion implantation process is conducted at an implant dose in a range from 1×10 14 atoms/cm 3 to 1×10 16 atoms/cm 3 .
7 . The method according to claim 1 , wherein the ion implantation process is conducted at a tilt angle in a range from 0° to 60°.
8 . The method according to claim 1 , wherein the ion implantation process is conducted at a twist angle in a range from 45° to 180°.
9 . The method according to claim 1 , wherein a top surface of the dielectric layer is formed with a recess having a depth in a range of greater than 0 nm and up to 80 nm.
10 . The method according to claim 1 , wherein the dimension of the dummy gate structure at a height in a range from ½ H to His increased after the ion implantation process, wherein H is a total height of the dummy gate structures.
11 . The method according to claim 1 , wherein the ion implantation process is conducted by ion implanting a dopant into the dummy gate structure, and the dopant includes nitrogen, argon, silicon, germanium, xenon, or combinations thereof.
12 . The method according to claim 1 , further comprising: forming a self-aligned contact layer on the conductive capping layer opposite to the metal gate, wherein the self-aligned contact layer has a width greater than a width of the lower portion of the conductive capping layer.
13 . A method for manufacturing a semiconductor device, comprising: forming a patterned structure on a substrate, the patterned structure including a dielectric layer, a dummy gate structure disposed in the dielectric layer, and a spacer layer which includes two lateral portions covering two opposite lateral surfaces of the dummy gate structure, and a top portion covering a top surface of the dummy gate structure, wherein the two lateral portions and the top portion of the spacer layer are formed integrally at the same time; reducing a dimension of the dummy gate structure by subjecting the dummy gate structure to an annealing process so as to modulate the dimension of the dummy gate structure to a desirable dimension; after the dimension of the dummy gate structure is modulated to the desirable dimension, removing the top portion of the spacer layer to form a pair of spacers; and removing the dummy gate structure to form a recess between the pair of spacers.
14 . The method according to claim 13 , wherein the annealing process is conducted at a temperature in a range from 500° C. to 1200° C.
15 . A method for manufacturing a semiconductor device, comprising: forming a patterned structure on a substrate, the patterned structure including a dielectric layer, a dummy gate structure disposed in the dielectric layer, and a spacer layer which includes two lateral portions covering two opposite lateral surfaces of the dummy gate structure, and a top portion covering a top surface of the dummy gate structure, wherein the two lateral portions and the top portion of the spacer layer are formed integrally at the same time; increasing a dimension of the dummy gate structure to an excess dimension by subjecting the dummy gate structure to an ion implantation process; reducing the excess dimension of the dummy gate structure by subjecting the dummy gate structure to an annealing process so as to modulate the excess dimension of the dummy gate structure to a desirable dimension; after the dimension of the dummy gate structure is modulated to the desirable dimension, removing the top portion of the spacer layer to form a pair of spacers; and removing the dummy gate structure to form a recess between the pair of spacers.
16 . The method according to claim 15 , wherein the ion implantation process is conducted by ion implanting a dopant into the dummy gate structure, and the dopant includes nitrogen, argon, silicon, germanium, xenon, or combinations thereof.
17 . The method according to claim 16 , wherein the dielectric layer is implanted by the dopant in the ion implantation process.
18 . The method according to claim 16 , wherein the ion implantation process is conducted at a tilt angle of greater than 0° and up to 60°.
19 . The method according to claim 17 , wherein the ion implantation process is conducted at a tilt angle in a range from 0° to 60°.
20 . The method according to claim 15 , wherein the annealing process includes a rapid thermal annealing process, a laser process, or a furnace annealing process.

Description

BACKGROUND In a method for manufacturing a semiconductor device, stress imbalance might be produced among poly gates (polysilicon gate electrodes), spacers, and an interlayer dielectric layer (for example, a silicon oxide layer), such that recesses formed by removing the poly gates have a bowing profile. Metal gates thus formed in the recesses might have voids or seams as a metal material fills into the recesses to form the metal gates, and might be detached during an etching back process. Therefore, the semiconductor device thus manufactured might have severe defects, and the yield of such semiconductor device might decrease significantly. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1 to 3 are schematic views illustrating some intermediate stages for producing metal gates in a method for manufacturing a semiconductor device. FIG. 4 is a flow diagram illustrating a method for manufacturing a semiconductor device in accordance with some embodiments. FIGS. 5 to 10 are schematic views illustrating some intermediate stages of the manufacturing method as depicted in FIG. 4 in accordance with some embodiments. FIG. 11 is a graph showing effects of an ion implantation process and an annealing process on gate critical dimension (CD) for gate profile modulation in the manufacturing method as depicted in FIG. 4. FIG. 12 is a graph showing effect of implant energy on the gate CD for the gate profile modulation in the manufacturing method as depicted in FIG. 4. FIG. 13 is a graph showing effect of implant dose on the gate CD for the gate profile modulation in the manufacturing method as depicted in FIG. 4. FIG. 14 is a schematic view illustrating a first ion implantation process for the gate profile modulation in the manufacturing method as depicted in FIG. 4; FIG. 15 is a schematic view illustrating a second ion implantation process for the gate profile modulation in the manufacturing method as depicted in FIG. 4; FIG. 16 is a schematic view illustrating definitions for a tilt angle (T) and a twist angle (W) of ion beam used in the ion implantation processes. FIG. 17 is a graph showing relationships between dopant concentration in a silicon oxide layer (an interlayer dielectric layer) and depth of the silicon oxide layer. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “over,” “below,” “upper,” “lower,” “upwardly,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Referring to the examples illustrated in FIGS. 1 to 3, in a method for manufacturing a semiconductor device, a process for forming metal gates 11 includes: forming a plurality of recesses 12 in a patterned structure 10 disposed on a substrate 1; forming a plurality of metal gates 11 respectively disposed in the recesses 12 and a plurality of gate dielectrics 13 respectively disposed in the recesses 12 to separate the metal gates 11 from the patterned structure 10; and etching back the metal gates 11 and the gate dielectrics 13. The patterned structure 10 includes at least one semiconductor fin 101 disposed on the substrate 1 (for example, a semiconductor substrate), a plurality of source/drain regions 102 disposed in the semiconductor fin 101 and spaced apart from ea