US-12628402-B2 - Semiconductor device with spacer and method for fabricating the same

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

Inventors

• JHEN-YU TSAI

Assignees

• NANYA TECHNOLOGY CORPORATION

Dates

Publication Date

20260512

Application Date

20231023

Claims (18)

1. 1 . A semiconductor device, comprising: a substrate; a plurality of word line structures positioned in the substrate; a buried conductive layer comprising: a bottom portion positioned in the substrate and between the plurality of word line structures; and a top portion positioned in the substrate, on the bottom portion, and between the plurality of word line structures; and an in-recess spacer positioned in the substrate, between the plurality of word line structures, surrounding the bottom portion, and covered by the top portion; wherein a top surface of the top portion, a top surface of the substrate, and top surfaces of the plurality of word line structures are substantially coplanar; wherein a bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar; wherein a sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.
2. 2 . The semiconductor device of claim 1 , wherein the plurality of word line structures respectively comprises: a word line dielectric layer inwardly positioned in the substrate and comprising a U-shaped cross-sectional profile; a bottom conductive layer positioned in the substrate and on the word line dielectric layer; and a word line capping layer positioned in the substrate and on the word line dielectric layer and the bottom conductive layer; wherein a bottom surface of the word line capping layer is at a vertical level lower than the bottom surface of the bottom portion.
3. 3 . The semiconductor device of claim 2 , wherein the plurality of word line structures respectively comprises: a middle conductive layer positioned between the bottom conductive layer and the word line capping layer.
4. 4 . The semiconductor device of claim 3 , wherein the plurality of word line structures respectively comprises: a bottom liner layer positioned between the bottom conductive layer and the middle conductive layer and between the middle conductive layer and the word line dielectric layer.
5. 5 . The semiconductor device of claim 4 , wherein the plurality of word line structures respectively comprises: a top conductive layer positioned between the word line capping layer and the middle conductive layer.
6. 6 . The semiconductor device of claim 5 , wherein the plurality of word line structures respectively comprises: a top liner layer positioned between the middle conductive layer and the top conductive layer and between the top conductive layer and the word line dielectric layer.
7. 7 . The semiconductor device of claim 6 , wherein the bottom liner layer and the top liner layer comprise a material including sp 2 hybridized carbon atoms.
8. 8 . The semiconductor device of claim 7 , wherein the word line capping layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or germanium oxide.
9. 9 . The semiconductor device of claim 8 , wherein the word line dielectric layer comprises a high-k material.
10. 10 . The semiconductor device of claim 9 , wherein the bottom conductive layer comprises titanium, titanium nitride, silicon, silicon germanium, or a combination thereof.
11. 11 . The semiconductor device of claim 10 , wherein the middle conductive layer comprises tungsten, tungsten nitride, or a combination thereof.
12. 12 . The semiconductor device of claim 11 , wherein the top conductive layer comprises molybdenum.
13. 13 . The semiconductor device of claim 12 , wherein a width ratio of a width of the bottom surface of the bottom portion to a width of the top surface of the top portion is between about 0.5 and about 0.95.
14. 14 . The semiconductor device of claim 12 , wherein a ratio of a thickness of the in-recess spacer to a width of the top surface of the top portion is between about 0.025 and about 0.25.
15. 15 . The semiconductor device of claim 12 , wherein a height ratio of a height of the in-recess spacer to a height of the buried conductive layer is between about 0.5 and about 0.85.
16. 16 . The semiconductor device of claim 12 , wherein the in-recess spacer has a square ring-shaped cross-sectional profile in a top-view perspective.
17. 17 . The semiconductor device of claim 12 , wherein the buried conductive layer has a square-shaped cross-sectional profile in a top-view perspective.
18. 18 . The semiconductor device of claim 12 , wherein the bottom liner layer and the top liner layer comprise the same material.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a divisional application of U.S. Non-Provisional application Ser. No. 18/219,238 filed Jul. 7, 2023, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with a spacer and a method for fabricating the semiconductor device with the spacer. DISCUSSION OF THE BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. SUMMARY One aspect of the present disclosure provides a semiconductor device including a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar. Another aspect of the present disclosure provide a semiconductor device including a substrate; a plurality of word line structures positioned in the substrate; a buried conductive layer including a bottom portion positioned in the substrate and between the plurality of word line structures, and a top portion positioned in the substrate, on the bottom portion, and between the plurality of word line structures; and an in-recess spacer positioned in the substrate, between the plurality of word line structures, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion, a top surface of the substrate, and top surfaces of the plurality of word line structures are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar. Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate; forming an opening in the substrate; conformally forming a layer of spacer material in the opening; performing a spacer etching process to remove a portion of the spacer material and form an in-recess spacer in the opening; and forming a buried conductive layer in the opening and covering the in-recess spacer. Due to the design of the semiconductor device of the present disclosure, the electrical field near the buried conductive layer may be reduced by employing the in-recess spacer. Therefore, the gate-induced drain leakage may be reduced due to the electrical field reduction. As a result, the performance of the semiconductor device may be improved. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not