US-12628403-B2 - Method of forming semiconductor structure

Abstract

A method of forming a semiconductor structure includes forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a BPSG layer on the second dielectric layer; etching the metal layer and the semiconductor layer; forming a first spacer layer on sidewalls of the semiconductor layer, the metal layer, and the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.

Inventors

• PEI-ROU JIANG
• Chih-Ching Lin

Assignees

• NANYA TECHNOLOGY CORPORATION

Dates

Publication Date

20260512

Application Date

20231206

Claims (20)

1. 1 . A method of forming a semiconductor structure, comprising: forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a boro-phospho-silicate-glass (BPSG) layer on the second dielectric layer; etching the metal layer and the semiconductor layer using the BPSG layer as a mask; forming a first spacer layer on a sidewall of the semiconductor layer, a sidewall of the metal layer, a sidewall of the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.
2. 2 . The method of forming the semiconductor structure of claim 1 , wherein the BPSG layer has a different etch selectivity from the first dielectric layer.
3. 3 . The method of forming the semiconductor structure of claim 1 , wherein a material of the first dielectric layer comprises silicon dioxide, and the first dielectric layer is formed by in-situ steam generation (ISSG).
4. 4 . The method of forming the semiconductor structure of claim 1 , wherein the top surface of the BPSG layer is convex after etching the metal layer and the semiconductor layer.
5. 5 . The method of forming the semiconductor structure of claim 1 , wherein forming the second spacer layer on the sidewall of the first spacer layer and the top surface of the second dielectric layer is performed such that the second spacer layer is in direct contact with the top surface of the second dielectric layer.
6. 6 . The method of forming the semiconductor structure of claim 1 , wherein a material of the second dielectric layer is different from a material of the first dielectric layer.
7. 7 . The method of forming the semiconductor structure of claim 1 , wherein a material of the first spacer layer is different from a material of the second spacer layer.
8. 8 . The method of forming the semiconductor structure of claim 1 , wherein a material of the first spacer layer is the same as a material of the second dielectric layer.
9. 9 . The method of forming the semiconductor structure of claim 1 , further comprising: detecting whether the top surface of the second dielectric layer is exposed during etching the second spacer layer; and stopping etching the second spacer layer when detecting the top surface of the second dielectric layer is exposed.
10. 10 . The method of forming the semiconductor structure of claim 1 , further comprising: forming a source/drain region in a position of the semiconductor substrate based on a thickness of the second spacer layer.
11. 11 . The method of forming the semiconductor structure of claim 1 , wherein a material of the semiconductor layer comprises polysilicon.
12. 12 . A method of forming a semiconductor structure, comprising: etching a metal layer and a semiconductor layer below the metal layer using a boro-phospho-silicate-glass (BPSG) layer as a mask, wherein the semiconductor layer is located between the metal layer and a first dielectric layer, and a second dielectric layer is located between the BPSG layer and the metal layer; forming a first spacer layer on a sidewall of the semiconductor layer, a sidewall of the metal layer, a sidewall of the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer, wherein the BPSG layer has a different etch selectivity from the first dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.
13. 13 . The method of forming the semiconductor structure of claim 12 , wherein a material of the first dielectric layer comprises silicon dioxide, and the first dielectric layer is formed by in-situ steam generation (ISSG).
14. 14 . The method of forming the semiconductor structure of claim 12 , wherein the top surface of the BPSG layer is convex after etching the metal layer and the semiconductor layer.
15. 15 . The method of forming the semiconductor structure of claim 12 , wherein forming the second spacer layer on the sidewall of the first spacer layer and the top surface of the second dielectric layer is performed such that the second spacer layer is in direct contact with the top surface of the second dielectric layer.
16. 16 . The method of forming the semiconductor structure of claim 12 , wherein a material of the second dielectric layer is different from a material of the first dielectric layer.
17. 17 . The method of forming the semiconductor structure of claim 12 , wherein a material of the first spacer layer is different from a material of the second spacer layer.
18. 18 . The method of forming the semiconductor structure of claim 12 , wherein a material of the first spacer layer is the same as a material of the second dielectric layer.
19. 19 . The method of forming the semiconductor structure of claim 12 , further comprising: detecting whether the top surface of the second dielectric layer is exposed during etching the second spacer layer; and stopping etching the second spacer layer when detecting the top surface of the second dielectric layer is exposed.
20. 20 . The method of forming the semiconductor structure of claim 12 , further comprising: forming a source/drain region in a position of a semiconductor substrate based on a thickness of the second spacer layer.

Description

BACKGROUND Field of Invention The present disclosure relates to a method of forming a semiconductor structure. Description of Related Art Metal-oxide-semiconductor field-effect transistors (MOSFETs) are commonly used in memory devices, including dynamic random access memory (DRAM) devices. A MOSFET is typically formed by providing a gate structure on a semiconductor substrate to define a channel region, and by forming source and drain regions on opposing sides of the channel region. In general, the formation of a typical gate structure may include forming a stack that includes a polysilicon layer, a metal layer, a nitride layer, and a top oxide layer; etching the polysilicon layer and the metal layer to form a gate stack using the top oxide layer as a mask; forming a nitride spacer on the sidewall of the gate stack; and forming an oxide spacer layer to cover the nitride spacer and the top oxide layer. Thereafter, the oxide spacer layer is etched to form an oxide spacer until the nitride layer is exposed. However, the remaining top oxide layer on the nitride layer and the oxide spacer layer have the same material (i.e., oxide), and thus the thickness of the remaining top oxide layer will affect end point detection (EPD) for controlling etching process time. As a result, the thickness of the oxide spacer is difficultly controlled due to the remaining top oxide layer, thereby causing unstable positions for source/drain regions implant, which results in poor electrical properties. SUMMARY According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a boro-phospho-silicate-glass (BPSG) layer on the second dielectric layer; etching the metal layer and the semiconductor layer using the BPSG layer as a mask; forming a first spacer layer on a sidewall of the semiconductor layer, a sidewall of the metal layer, a sidewall of the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer. In some embodiments, the BPSG layer has a different etch selectivity from the first dielectric layer. In some embodiments, a material of the first dielectric layer includes silicon dioxide, and the first dielectric layer is formed by in-situ steam generation (ISSG). In some embodiments, the top surface of the BPSG layer is convex after etching the metal layer and the semiconductor layer. In some embodiments, forming the second spacer layer on the sidewall of the first spacer layer and the top surface of the second dielectric layer is performed such that the second spacer layer is in direct contact with the top surface of the second dielectric layer. In some embodiments, a material of the second dielectric layer is different from a material of the first dielectric layer. In some embodiments, a material of the first spacer layer is different from a material of the second spacer layer. In some embodiments, a material of the first spacer layer is the same as a material of the second dielectric layer. In some embodiments, method of forming the semiconductor structure further includes detecting whether the top surface of the second dielectric layer is exposed during etching the second spacer layer; and stopping etching the second spacer layer when detecting the top surface of the second dielectric layer is exposed. In some embodiments, the method of forming the semiconductor structure further includes forming a source/drain region in a position of the semiconductor substrate based on a thickness of the second spacer layer. In some embodiments, a material of the semiconductor layer includes polysilicon. According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes etching a metal layer and a semiconductor layer below the metal layer using a boro-phospho-silicate-glass (BPSG) layer as a mask, wherein the semiconductor layer is located between the metal layer and a first dielectric layer, and a second dielectric layer is located between the BPSG layer and the metal layer; forming a first spacer layer on a sidewall of the semiconductor layer, a sidewall of the metal layer, a sidewall of the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer, wherein the BPSG layer has a different etch selectivity from the first dielectric layer; forming a second spacer layer on a