US-12628404-B2 - Semiconductor device

Abstract

A semiconductor device includes a substrate including an active region, a first gate line and a second gate line in the active region, a first source/drain contact pattern in the active region at one side of the first gate line, a second source/drain contact pattern in the active region at one side of the second gate line, and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line. The first gate line and the second gate line may be spaced apart from each other in the first direction and may extend in the second direction. The second direction may cross the first direction. A size of the dummy source/drain contact pattern may be less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern.

Inventors

• Taehun MYUNG
• Yuri Masuoka
• Kihwang Son
• Jaehun Jeong
• SeulKi PARK
• Joongwon Jeon
• Kyunghoon JUNG
• Yonghyun KO
• Seungwook Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230309

Priority Date

20220310

Claims (20)

1. 1 . A semiconductor device comprising: a substrate including an active region; a first gate line and a second gate line in the active region, the first gate line and the second gate line being spaced apart from each other in a first direction and extending in a second direction, the second direction crossing the first direction; a first source/drain contact pattern in the active region at one side of the first gate line; a second source/drain contact pattern in the active region at one side of the second gate line; and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line, wherein a greatest length of the dummy source/drain contact pattern in the second direction is less than a greatest length of the first source/drain contact pattern in the second direction and a greatest length of the second source/drain contact pattern in the second direction, and wherein the dummy source/drain contact pattern, the first source/drain contact pattern, and the second source/drain contact pattern have substantially quadrilateral shapes in a cross-sectional view.
2. 2 . The semiconductor device of claim 1 , wherein the dummy source/drain contact pattern is spaced apart in the second direction from a first edge of the active region, a second edge of the active region, or both the first edge of the active region and the second edge of the active region.
3. 3 . The semiconductor device of claim 1 , wherein the dummy source/drain contact pattern includes a plurality of dummy source/drain contact patterns, and sizes of the plurality of dummy source/drain contact patterns are less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern.
4. 4 . The semiconductor device of claim 1 , wherein the active region includes a dummy contact region between the first gate line and the second gate line, the dummy contact region includes a dummy source/drain region in the substrate, and the active region includes a dummy source/drain loss region in the dummy source/drain region below the dummy source/drain contact pattern.
5. 5 . The semiconductor device of claim 1 , wherein the dummy source/drain contact pattern has a first pattern width in the first direction, the first source/drain contact pattern has a second pattern width in the first direction, the second source/drain contact pattern has a third pattern width in the first direction, and the first pattern width is equal to the second pattern width and the third pattern width.
6. 6 . The semiconductor device of claim 5 , wherein the active region has a first region width in the first direction and a first region length in the second direction, the greatest length of the dummy source/drain contact pattern in the second direction is less than the first region length, and the greatest lengths of the first source/drain contact pattern and the second source/drain contact pattern in the second direction are equal to the first region length.
7. 7 . The semiconductor device of claim 1 , wherein the dummy source/drain contact pattern has a first pattern width in the first direction, the first source/drain contact pattern has a second pattern width in the first direction, the second source/drain contact pattern has a third pattern width in the first direction, and the first pattern width is less than the second pattern width and the third pattern width.
8. 8 . The semiconductor device of claim 7 , wherein the active region has a first region width in the first direction and a first region length in the second direction, the greatest length of the dummy source/drain contact pattern in the second direction is less than the first region length, and the greatest lengths of the first source/drain contact pattern and the second source/drain contact pattern in the second direction are equal to the first region length.
9. 9 . The semiconductor device of claim 1 , wherein the dummy source/drain contact pattern includes a plurality of sub-dummy source/drain contact patterns spaced apart from each other.
10. 10 . The semiconductor device of claim 1 , wherein the first gate line and the second gate line include a planar gate line or a trench-type gate line.
11. 11 . The semiconductor device of claim 1 , wherein the active region includes a fin-type active region, and the first gate line and the second gate line include a planar gate line or a trench-type gate line.
12. 12 . A semiconductor device comprising: a substrate including an active region having a first region width in a first direction and a first region length in a second direction, the second direction perpendicular to the first direction, wherein the active region comprises a continuous region bounded laterally by insulating regions, the active region including a first active contact region, a second active contact region, and a dummy contact region between the first active contact region and the second active contact region; a first gate line and a second gate line extending in the second direction in the active region, the second gate line spaced apart from the first gate line in the first direction, the first gate line and the second gate line in the active region with the first active contact region at one side of the first gate line, the second active contact region at one side of the second gate line, and the dummy contact region between the first gate line and the second gate line; a first source/drain contact pattern in the first active contact region, the first source/drain contact pattern being spaced apart from the first gate line in the first direction; a second source/drain contact pattern in the second active contact region, the second source/drain contact pattern being spaced apart from the second gate line in the first direction; and a dummy source/drain contact pattern in the dummy contact region between the first gate line and the second gate line, wherein the first source/drain contact pattern and the second source/drain contact pattern each extend to a first edge of the active region and a second edge of the active region, wherein the first edge and the second edge are opposite edges in the second direction, and wherein the dummy source/drain contact pattern is spaced apart from at least one of the first edge or the second edge in the second direction.
13. 13 . The semiconductor device of claim 12 , wherein the first active contact region and the second active contact region include a source/drain region in the substrate.
14. 14 . The semiconductor device of claim 12 , wherein the first source/drain contact pattern has a second pattern width in the first direction and a second pattern length in the second direction, the second source/drain contact pattern has a third pattern width in the first direction and a third pattern length in the second direction, the first region length is equal to the second pattern length and the third pattern length, and the first region width is greater than the second pattern width and the third pattern width.
15. 15 . The semiconductor device of claim 12 , wherein the dummy contact region includes a dummy source/drain region in the substrate, and a dummy source/drain loss region is not formed in the dummy source/drain region.
16. 16 . A semiconductor device comprising: a substrate including an active region, the active region including a first active contact region, a second active contact region, and a plurality of dummy contact regions in the active region; a plurality of gate lines spaced apart from each other in a first direction in the active region, the plurality of gate lines extending in a second direction perpendicular to the first direction in the active region, the plurality of gate lines including a first gate line and a second gate line, the plurality of gate lines in the active region with the first active contact region at one side of the first gate line and the second active contact region at one side of the second gate line, and the plurality of dummy contact regions in the active region between the plurality of gate lines; a first source/drain contact pattern in the first active contact region; a second source/drain contact pattern in the second active contact region; and a plurality of dummy source/drain contact patterns in at least one of the plurality of dummy contact regions, wherein greatest lengths of the plurality of dummy source/drain contact patterns in the second direction are less than a greatest length of the first source/drain contact pattern in the second direction and a greatest length of the second source/drain contact pattern in the second direction, and wherein the plurality of dummy source/drain contact patterns, the first source/drain contact pattern, and the second source/drain contact pattern have substantially quadrilateral shapes in a cross-sectional view.
17. 17 . The semiconductor device of claim 16 , wherein the plurality of dummy source/drain contact patterns are spaced apart in the second direction from a first edge of the active region, a second edge of the active region, or both the first edge of the active region and the second edge of the active region.
18. 18 . The semiconductor device of claim 16 , wherein the plurality of dummy source/drain contact patterns have different pattern widths in the first direction.
19. 19 . The semiconductor device of claim 16 , wherein the plurality of dummy source/drain contact patterns have first pattern widths in the first direction, the first source/drain contact pattern has a second pattern width in the first direction, the second source/drain contact pattern has a third pattern width in the first direction, and each of the first pattern widths is equal to the second pattern width and the third pattern width.
20. 20 . The semiconductor device of claim 16 , wherein the plurality of dummy source/drain contact patterns have first pattern widths in the first direction, the first source/drain contact pattern has a second pattern width in the first direction, the second source/drain contact pattern has a third pattern width in the first direction, and each of the first pattern widths is less than the second pattern width and the third pattern width.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0030325, filed on Mar. 10, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Inventive concepts relate to a semiconductor device, and more particularly, to a semiconductor device with improved device performance. In line with the miniaturization of semiconductor devices, patterns included in the semiconductor devices have gradually been miniaturized. When manufacturing a semiconductor device, a micro-patterning process for forming micro-patterning becomes increasingly difficult. Accordingly, there may be a need for a method for overcoming difficulties in the micro-patterning process and improving the device performance of miniaturized semiconductor devices. SUMMARY Inventive concepts provide a semiconductor device with improved device performance. According to an example embodiment of inventive concepts, a semiconductor device may include a substrate including an active region in a substrate; a first gate line and a second gate line in the active region, the first gate line and the second gate line being spaced apart from each other in a first direction and extending in a second direction, the second direction crossing the first direction; a first source/drain contact pattern in the active region at one side of the first gate line; a second source/drain contact pattern in the active region at one side of the second gate line; and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line. A size of the dummy source/drain contact pattern may be less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern. According to an example embodiment of inventive concepts, a semiconductor device may include a substrate including an active region having a first region width in a first direction and a first region length in a second direction, the second direction perpendicular to the first direction, the active region including a first active contact region, a second active contact region, and a dummy contact region between the first active contact region and the second active contact region; a first gate line and a second gate line extending in the second direction in the active region, the second gate line spaced apart from the first gate line in the first direction, the first gate line and the second gate line in the active region with the first active contact region at one side of the first gate line, the second active contact region at one side of the second gate line, and the dummy contact region between the first gate line and the second gate line; a first source/drain contact pattern in the first active contact region, the first source/drain contact pattern being spaced apart from the first gate line in the first direction; and a second source/drain contact pattern in the second active contact region, the second source drain/contact pattern being spaced apart from the second gate line in the first direction. According to another example embodiment of inventive concepts, a semiconductor device may include a substrate including an active region, the active region including a first active contact region, a second active contact region, and a plurality of dummy contact regions in the active region; a plurality of gate lines spaced apart from each other in a first direction in the active region, the plurality of gate lines extending in a second direction perpendicular to the first direction in the active region, the plurality of gate lines including a first gate line and a second gate line, the plurality of gate lines in the active region with the first active contact region disposed at one side of the first gate line and the second active contact region at one side of the second gate line, and the plurality of dummy contact regions in the active region between the plurality of gate lines; a first source/drain contact pattern in the first active contact region; a second source/drain contact pattern in the second active contact region; and a plurality of dummy source/drain contact patterns in at least one of the plurality of dummy contact regions. Sizes of the plurality of dummy source/drain contact patterns may be less than a size of the first source/drain contact pattern and a size the second source/drain contact pattern. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIGS. 1 and 2 are plan views of a semiconductor device according to an embodiment of inventive concepts; FIG. 3 is a cross-sectional view of a semiconductor device according to an embodiment of inventive concepts; FIG. 4 is a diagram illustrating device resistance