US-12628406-B2 - Performance optimization by sizing gates and source/drain contacts differently for different transistors

Abstract

A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.

Inventors

• Li-Hui Chen
• Chun-Hung Chen
• Jhon Jhy Liaw

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20220831

Claims (20)

1. 1 . A device, comprising: a first transistor that comprises a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain, wherein: the first gate has a first dimension measured in a first lateral direction, and the first source/drain contact has a second dimension measured in the first lateral direction; and a second transistor that comprises a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain, wherein: the second gate has a third dimension measured in the first lateral direction, the second source/drain contact has a fourth dimension measured in the first lateral direction, a first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension; the first transistor is a part of an electronic memory storage device; the second transistor is a part of a logic device that is not the electronic memory storage device; the first dimension is greater than the third dimension; and the second dimension is less than the fourth dimension.
2. 2 . The device of claim 1 , wherein: the electronic memory storage device comprises a static random access memory (SRAM) cell; and the logic device comprises a controller for operating the SRAM cell.
3. 3 . The device of claim 1 , wherein the first ratio is greater than the second ratio.
4. 4 . The device of claim 1 , wherein the first transistor and the second transistor have different operational speeds.
5. 5 . The device of claim 1 , wherein: the first transistor is implemented in a first region of a wafer; the second transistor is implemented in a second region of the wafer; and the first region of the wafer and the second region of the wafer have different pattern densities.
6. 6 . The device of claim 1 , wherein: the first gate is separated from the first source/drain contact by a first distance in the first lateral direction; the second gate is separated from the second source/drain contact by a second distance in the first lateral direction; and the first distance is substantially equal to the second distance.
7. 7 . A device, comprising: a first gate disposed over a substrate; a first source/drain disposed in a first portion of the substrate adjacent to the first gate; a first source/drain contact disposed over the first source/drain; a second gate disposed over the substrate; a second source/drain disposed in a second portion of the substrate adjacent to the second gate; and a second source/drain contact disposed over the second source/drain; wherein: the first gate is wider than the second gate in a first horizontal direction; the first source/drain contact is narrower than the second source/drain contact in the first horizontal direction; the first gate and the first source/drain are components of a first type of transistor; the second gate and the second source/drain are components of a second type of transistor different from the first type of transistor; the first type of transistor is part of a memory device; and the second type of transistor is part of a non-memory device.
8. 8 . The device of claim 7 , wherein: the memory device comprises a Static Random Access Memory (SRAM) device; and the non-memory device is a part of a microcontroller configured to control an operation of the SRAM device.
9. 9 . The device of claim 7 , wherein: the first type of transistor has a first operational speed; and the second type of transistor has a second operational speed different from the first operational speed.
10. 10 . The device of claim 7 , wherein: the first gate and the first source/drain are implemented in a first region of the substrate; the second gate and the second source/drain are implemented in a second region of the substrate; and the first region of the substrate and the second region of the substrate have different pattern densities.
11. 11 . The device of claim 7 , further comprising: a first gate spacer disposed between the first gate and the first source/drain; and a second gate spacer disposed between the second gate and the second source/drain; wherein the first gate spacer and the second gate spacer have substantially similar widths.
12. 12 . The device of claim 7 , further comprising: a first gate spacer disposed between the first gate and the first source/drain; and a second gate spacer disposed between the second gate and the second source/drain, wherein a width of the first gate spacer is equal to a width of the second gate spacer in the first horizontal direction.
13. 13 . A device, comprising: a first gate disposed over a substrate; a first source/drain disposed in a first portion of the substrate adjacent to the first gate; a first source/drain contact disposed over the first source/drain; a second gate disposed over the substrate; a second source/drain disposed in a second portion of the substrate adjacent to the second gate; and a second source/drain contact disposed over the second source/drain; wherein: the first gate is wider than the second gate in a first horizontal direction; the first source/drain contact is narrower than the second source/drain contact in the first horizontal direction; the first gate and the first source/drain are components of a first type of transistor; the second gate and the second source/drain are components of a second type of transistor different from the first type of transistor; the first type of transistor is part of a non-memory device; and the second type of transistor is part of a memory device.
14. 14 . The device of claim 13 , wherein: the memory device comprises a Static Random Access Memory (SRAM) device.
15. 15 . The device of claim 14 , wherein: the non-memory device is a part of a microcontroller configured to control an operation of the SRAM device.
16. 16 . The device of claim 13 , wherein: the first type of transistor has a first operational speed; and the second type of transistor has a second operational speed different from the first operational speed.
17. 17 . The device of claim 13 , wherein: the first gate and the first source/drain are implemented in a first region of the substrate; the second gate and the second source/drain are implemented in a second region of the substrate; and the first region of the substrate and the second region of the substrate have different pattern densities.
18. 18 . The device of claim 13 , further comprising: a first gate spacer disposed between the first gate and the first source/drain; and a second gate spacer disposed between the second gate and the second source/drain; wherein the first gate spacer and the second gate spacer have substantially similar widths.
19. 19 . The device of claim 13 , further comprising: a first gate spacer disposed between the first gate and the first source/drain; and a second gate spacer disposed between the second gate and the second source/drain, wherein a width of the first gate spacer is equal to a width of the second gate spacer in the first horizontal direction.
20. 20 . The device of claim 13 , further comprising: an interlayer dielectric overlying the first source/drain and in contact with the first source/drain.

Description

BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. For example, as semiconductor devices continue to get scaled down, the space between the gate and source/drain contact becomes smaller, which could lead to inadvertent electrical shorting between the gate and source/drain contact. As another example, the scaling down of semiconductor devices may cause electrical current leakage. As a further example, the scaling down of semiconductor devices may increase parasitic resistance. These issues are undesirable, since they may degrade device performance or even cause device failures. Unfortunately, conventional devices and their method of fabrication have not optimized the transistors to sufficiently address these issues. Therefore, although conventional methods of fabricating semiconductor devices have generally been adequate, they have not been satisfactory in all aspects. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a perspective view of an IC device in the form of a FinFET according to various aspects of the present disclosure. FIG. 1B is a planar top view of an IC device in the form of a FinFET according to various aspects of the present disclosure. FIG. 1C is a perspective view of an IC device in the form of a GAA device according to various aspects of the present disclosure. FIGS. 2A-2B illustrate an original IC layout design and a revised IC layout design, respectively, according to various aspects of the present disclosure. FIGS. 3A-16A are X-cut cross-sectional side views of various embodiments of IC devices at various stages of fabrication according to various aspects of the present disclosure. FIGS. 3B-10B are Y-cut cross-sectional side views of various embodiments of IC devices at various stages of fabrication according to various aspects of the present disclosure. FIG. 17 is a circuit schematic of an SRAM cell according to various aspects of the present disclosure. FIG. 18 is a block diagram of a manufacturing system according to various aspects of the present disclosure. FIG. 19 is a flowchart illustrating a method of revising an IC layout design according to various aspects of the present disclosure. FIG. 20 is a flowchart illustrating a method of fabricating a semiconductor device according to various aspects of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct co