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US-12628409-B2 - Multi-threshold voltage integration scheme for semiconductor devices

US12628409B2US 12628409 B2US12628409 B2US 12628409B2US-12628409-B2

Abstract

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and V t requirements (including multi-V t ), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.

Inventors

  • Srinivas Gandikota
  • Tengzhou Ma
  • Geetika Bajaj
  • Debaditya Chatterjee
  • Hsin-Jung Yu
  • Pei Hsuan Lin
  • YIXIONG YANG

Assignees

  • APPLIED MATERIALS, INC.

Dates

Publication Date
20260512
Application Date
20230428

Claims (18)

  1. 1 . A method of manufacturing an electronic device, the method comprising: forming a P-dipole stack and an N-dipole stack on a semiconductor substrate, each of the P-dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the semiconductor substrate, forming each of the P-dipole stack and the N-dipole stack comprising sequentially: depositing an interfacial layer on the top surface of the channel; depositing a hafnium-containing layer on the interfacial layer, the hafnium-containing layer having a thickness of less than or equal to 5 Å; depositing a dipole layer on the hafnium-containing layer; selectively etching the dipole layer from one of the P-dipole stack or the N-dipole stack and increasing a thickness of the dipole layer on the other of the P-dipole stack or the N-dipole stack to form multiple threshold voltages (multi-V t ); and depositing a high-κ dielectric layer having a thickness in a range of from 10 Å to 20 Å on the dipole layer.
  2. 2 . The method of claim 1 , wherein the interfacial layer comprises a silicon oxide (SiOx) layer formed on doped silicon or undoped silicon.
  3. 3 . The method of claim 1 , wherein the hafnium-containing layer comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), nitrogen-doped hafnium oxide (HfOx), or nitrogen-doped hafnium zirconium oxide (HfZrOx).
  4. 4 . The method of claim 1 , wherein the hafnium-containing layer has a thickness of less than or equal to 3 Å.
  5. 5 . The method of claim 1 , wherein the high-κ dielectric layer comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).
  6. 6 . The method of claim 1 , wherein depositing the dipole layer comprises exposing the semiconductor substrate to a pulse of a metal-containing precursor and a pulse of a reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.
  7. 7 . The method of claim 6 , wherein the metal-containing comprises one or more of titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).
  8. 8 . The method of claim 6 , wherein the reactant comprises ammonia (NH 3 ).
  9. 9 . The method of claim 6 , wherein the dipole layer comprises lanthanum nitride (LaN) or aluminum nitride (AlN).
  10. 10 . The method of claim 1 , further comprising annealing the P-dipole stack and the N-dipole stack at a temperature of less than or equal to 1000° C. to drive in metal atoms from the dipole layer and densify the high-κ dielectric layer to form an annealed high-κ dielectric layer.
  11. 11 . The method of claim 10 , further comprising depositing a work-function layer on the annealed high-κ dielectric layer.
  12. 12 . The method of claim 1 , wherein the method improves a threshold voltage (V t ) of the electronic device compared to a method that does not include forming a hafnium-containing layer having a thickness of less than or equal to 5 Å on the interfacial layer.
  13. 13 . The method of claim 1 , wherein the method reduces leakage (J g ) of the electronic device compared to a method that does not include forming a hafnium-containing layer having a thickness of less than or equal to 5 Å on the interfacial layer.
  14. 14 . A method of manufacturing an electronic device, the method comprising: forming a P-dipole stack and an N-dipole stack on a semiconductor substrate, each of the P-dipole stack and the N-dipole stack formed on a top surface of a channel located between a source and a drain on the semiconductor substrate, forming each of the P-dipole stack and the N-dipole stack comprising sequentially: depositing an interfacial layer on the top surface of the channel, the interfacial layer comprising silicon oxide (SiOx); depositing a hafnium-containing layer on the interfacial layer, the hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å; depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer; selectively etching the dipole layer from one of the P-dipole stack or the N-dipole stack and increasing a thickness of the dipole layer on the other of the P-dipole stack or the N-dipole stack to form multiple threshold voltages (multi-V t ); and depositing a high-κ dielectric layer having a thickness in a range of from 10 Å to 20 Å on the dipole layer.
  15. 15 . The method of claim 14 , wherein the high-κ dielectric layer comprises one or more of hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).
  16. 16 . The method of claim 14 , further comprising annealing the P-dipole stack and the N-dipole stack at a temperature of less than or equal to 1000° C. to drive in metal atoms from the dipole layer and densify the high-κ dielectric layer to form an annealed high-κ dielectric layer.
  17. 17 . The method of claim 16 , further comprising depositing a work-function layer on the annealed high-κ dielectric layer.
  18. 18 . The method of claim 14 , wherein the method reduces leakage (J g ) of the electronic device compared to a method that does not include forming a hafnium-containing layer having a thickness of less than or equal to 5 Å on the interfacial layer.

Description

TECHNICAL FIELD Embodiments of the present disclosure pertain to the field of electronic device manufacturing, and in particular, to transistors. More particularly, embodiments of the disclosure are directed to FinFET and GAA devices and methods of manufacturing FinFET and GAA devices. BACKGROUND Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. Transistors are circuit components or elements that are often formed on semiconductor devices. Many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. Integrated circuits incorporate planar field-effect transistors (FETs) in which current flows through a semiconducting channel between a source and a drain, in response to a voltage applied to a control gate. As device dimensions have shrunk, device geometries and materials have experienced difficulty maintaining switching speeds without incurring failures. Several new technologies emerged that allowed chip designers to continue shrinking gate lengths. Control of the dimensions of device structure is a key challenge for present and future technology generations. Shrinking of the materials currently used as negative metal-oxide-semiconductor (N-MOS) transistors and positive metal-oxide-semiconductor (P-MOS) transistors have become a challenge due to change in basic properties, such as threshold voltage (Vt). Additionally, the migration of transistor technology from planar FET to FinFET to GAA devices requires conformal work-function layers for multiple threshold voltages (multi-Vt). The Vt tuning range will be limited by the film thickness variation with further scaling down of device sizes. There are also challenges associated with conventional dipole engineering techniques. To achieve the desired dipole effect, the desired element is driven from a deposited film with spike anneal and removed after drive in. The spike anneal can potentially cause an equivalent oxide thickness (EOT) penalty and high thermal budget because free oxygen atoms in the gate dielectric layers and the overlaying dipole stack diffuse downward to oxidize the underlying silicon layer. Additionally, precise control of the amount of dipole species in metal gate stacks, such as high-K metal gate stacks, is crucial to achieve desired Vt (or multi-Vt) for transistors. Conventional processes include “dipole first” processes and “dipole last” processes. Typically, dipole first processes include flowing a metal-containing precursor and a reactant over an interfacial layer to deposit metal atoms on the interfacial layer (forming a treated interfacial layer) to achieve desired dipole effect, followed by depositing a high-K dielectric layer on the treated interfacial layer. Dipole last processes typically include forming an interfacial layer on a substrate, forming a high-K dielectric layer on the interfacial layer, flowing a metal-containing precursor and a reactant over the high-K dielectric layer to deposit metal atoms on the high-K dielectric layer, and annealing the substrate to drive the metal atoms into an interface of the interfacial layer and the high-K dielectric layer to achieve desired dipole effect. In dipole last processes, instead of forming an ultrathin surface adsorption layer, an atomic layer deposition (ALD) process is performed to deposit a dipole layer having a thickness in a range of from 3 Å to 20 Å that contains the metal atoms, usually in their oxide or nitride form. A capping material is typically needed on top of the dipole oxide/nitride layer to avoid silicon oxide regrowth during the annealing process. Conventional dipole first processes allow for Vt tunability of greater than about 200 millivolts (mV), while conventional dipole last processes allow for Vt tunability of less than about 200 mV. Accordingly, in conventional dipole last processes, multiple annealing steps would be required to reach an increased Vt, such as the Vt achieved by a conventional dipole first process. By switching to a conventional dipole first process for greater Vt tunability, multi-Vt capability is lost because there are currently no known etch processes which can selectively remove dipole materials without removing a portion of the silicon oxide (SiOx) interfacial layer. Also, particularly in dipole first processes, there are challenges associated with Vt shift and leakage. Accordingly, there is a need for improved methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and