US-12628410-B2 - Non-shared metal gate integration for scaled gate all around (GAA) transistors

US12628410B2US 12628410 B2US12628410 B2US 12628410B2US-12628410-B2

Abstract

Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.

Inventors

Ruqiang Bao
Effendi Leobandung
Eric Miller
Charlotte DeWan Adams
Cornelius Brown Peethala
Liqiao QIN

Assignees

INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date: 20260512
Application Date: 20220901

Claims (14)

1 . A method for forming a semiconductor device, the method comprising: forming a first nanosheet stack in a first region of a substrate and a second nanosheet stack in a second region of the substrate; forming a first work function metal stack around one or more nanosheets in the first nanosheet stack and one or more nanosheets in the second nanosheet stack; forming a first sacrificial material around the first work function metal stack in the first nanosheet stack and the first work function metal stack in the second nanosheet stack; replacing the first sacrificial material in the second nanosheet stack with a second sacrificial material; replacing the first sacrificial material and the first work function metal stack in the first nanosheet stack with a second work function metal stack; and replacing the second sacrificial material in the second nanosheet stack with a third work function metal stack.
2 . The method of claim 1 , wherein the first work function metal stack pinches off a space between vertically adjacent nanosheets.
3 . The method of claim 1 , wherein a portion of the first sacrificial material pinches off a space between vertically adjacent nanosheets.
4 . The method of claim 1 , wherein replacing the first sacrificial material in the second nanosheet stack with the second sacrificial material comprises: removing the first sacrificial material from the second nanosheet stack; and forming the second sacrificial material around the first work function metal stack in the second nanosheet stack.
5 . The method of claim 1 , wherein replacing the first sacrificial material and the first work function metal stack in the first nanosheet stack with the second work function metal stack comprises: removing the first sacrificial material and the first work function metal stack from the first nanosheet stack; and forming the second work function metal stack around the one or more nanosheets in the first nanosheet stack.
6 . The method of claim 1 , wherein replacing the second sacrificial material in the second nanosheet stack with the third work function metal stack comprises: removing the second sacrificial material from the second nanosheet stack; and forming a third work function metal stack around the first work function metal stack in the second nanosheet stack.
7 . The method of claim 1 , wherein the first region of the substrate comprises an nFET region and the second region of the substrate comprises a pFET region.
8 . A method for forming a semiconductor device, the method comprising: forming a first semiconductor structure in a first region of a substrate, the first semiconductor structure comprising a first gate in a non-shared metal gate integration; and forming a second semiconductor structure in a second region of the substrate, the second semiconductor structure comprising a second gate in the non-shared metal gate integration; wherein the second gate comprises a first work function metal stack and a third work function metal stack; wherein the first gate comprises a second work function metal stack; and wherein gate dielectrics are shared between the first gate and the second gate.
9 . The method of claim 8 , wherein the non-shared metal gate integration is structured such that no work function metal stacks are shared between the first semiconductor structure and the second semiconductor structure.
10 . The method of claim 8 , wherein the second work function metal stack in the first gate comprises a same material as one of the first work function metal stack and the third work function metal stack in the second gate, but the work function metals having a same material are not continuous across the first semiconductor structure and the second semiconductor structure.
11 . The method of claim 10 , wherein the first gate and the second gate comprises a continuous gate layout.
12 . The method of claim 8 , wherein the first semiconductor structure comprises a first nanosheet stack and the first region comprises an nFET region, and the second semiconductor structure comprises a second nanosheet stack and the second region comprises a pFET region.
13 . The method of claim 12 , wherein the first work function metal stack pinches off a space between vertically adjacent nanosheets in the second nanosheet stack.
14 . The method of claim 8 , wherein the first semiconductor structure comprises one or more semiconductor fins and the second semiconductor structure comprises one or more semiconductor fins.

Description

BACKGROUND The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to processing methods and resulting structures for a non-shared metal gate integration of scaled gate all around (GAA) transistors. Known metal oxide semiconductor field effect transistor (MOSFET) fabrication techniques include process flows for constructing planar field effect transistors (FETs). A planar FET includes a substrate (also referred to as a silicon slab); a gate formed over the substrate; source and drain regions formed on opposite ends of the gate; and a channel region near the surface of the substrate under the gate. The channel region electrically connects the source region to the drain region while the gate controls the current in the channel. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”). In recent years, research has been devoted to the development of nonplanar transistor architectures. For example, GAA transistors (also referred to as nanosheet FETs and nanowire FETs) include a non-planar architecture that provides increased device density and some increased performance over lateral devices. In nanosheet FETs, in contrast to conventional planar FETs, the channel is implemented as a plurality of stacked and spaced-apart nanosheets. The gate stack wraps around the full perimeter of each nanosheet, thus enabling fuller depletion in the channel region, and also reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL). SUMMARY Embodiments of the invention are directed to a method for forming a semiconductor device with a non-shared metal gate integration. A non-limiting example of the method includes forming a first nanosheet stack in a first region of a substrate and a second nanosheet stack in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack. Embodiments of the invention are directed to a method for forming a semiconductor device with a non-shared metal gate integration. A non-limiting example of the method includes forming a first semiconductor structure in a first region of a substrate having a first gate and a second semiconductor structure in a second region of the substrate having a second gate. In some embodiments, the second gate includes a first work function metal stack and a third work function metal stack and the first gate includes a second work function metal stack. In some embodiments, no work function metal stacks are shared between the first semiconductor structure and the second semiconductor structure, while gate dielectrics are shared between the first gate and the second gate. Embodiments of the invention are directed to a semiconductor structure. A non-limiting example of the semiconductor structure includes a first semiconductor structure in a first region of a substrate. The first semiconductor structure includes a first gate formed over channel regions of the first semiconductor structure. A second semiconductor structure is in a second region of the substrate. The second semiconductor structure includes a second gate formed over channel regions of the second semiconductor structure. The second gate includes a first work function metal stack and a third work function metal stack and the first gate includes a second work function metal stack. The semiconductor structure includes a non-shared work function metal integration, such that no work function metal stacks are shared between the first semiconductor structure and the second semiconductor structure and such that gate dielectrics are shared between the first gate and the second gate. Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompany