US-12628411-B2 - Method of forming confined growth S/D contact defined by sidewall constraints with selective deposition of inner spacer for CFET

Abstract

A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. The channel structures have opposing ends that are uncovered. Sidewall constraints are formed at the opposing ends of the channel structures. Each pair of the sidewall constraints laterally bounds a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region. S/D structures are formed on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.

Inventors

• Jeffrey Smith

Assignees

• TOKYO ELECTRON LIMITED

Dates

Publication Date

20260512

Application Date

20230519

Claims (20)

1. 1 . A method of manufacturing a semiconductor device, the method comprising: forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material; forming fin structures from the stack, the fin structures including channel structures formed of the first semiconductor material, the channel structures having opposing ends that are uncovered; forming sidewall constraints at the opposing ends of the channel structures, each pair of the sidewall constraints including two respective sidewall constraints that are separate from each other to laterally bound a respective source/drain (S/D) region at a respective end of the channel structures and to define a respective top opening between the two respective sidewall constraints for accessing the respective S/D region; and forming S/D structures on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.
2. 2 . The method of claim 1 , further comprising: removing exposed portions of the fin structures between each pair of the sidewall constraints via the respective top opening.
3. 3 . The method of claim 2 , further comprising: forming recesses in the second semiconductor material; and forming inner spacers in the recesses.
4. 4 . The method of claim 3 , further comprising: recessing the first semiconductor material after forming the inner spacers.
5. 5 . The method of claim 3 , further comprising: depositing the inner spacers on the second semiconductor material selectively, relative to the first semiconductor material, to form the inner spacers.
6. 6 . The method of claim 1 , further comprising: forming a constraint material covering the fin structures, the constraint material including the sidewall constraints and top constraints covering S/D regions.
7. 7 . The method of claim 6 , further comprising: removing the top constraints of the constraint material selectively, relative to the sidewall constraints, to uncover the S/D regions.
8. 8 . The method of claim 6 , further comprising: forming the constraint material conformally over the fin structures.
9. 9 . The method of claim 1 , wherein: the sidewall constraints laterally confine the third semiconductor material when epitaxially growing the third semiconductor material.
10. 10 . A method of manufacturing a semiconductor device, the method comprising: forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material; forming fin structures from the stack, the fin structures including channel structures formed of the first semiconductor material, the channel structures having opposing ends that are uncovered; forming sidewall constraints at the opposing ends of the channel structures, each pair of the sidewall constraints laterally bounding a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region; and forming S/D structures on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints, wherein the third semiconductor material is epitaxially grown to a height below a top of the sidewall constraints.
11. 11 . The method of claim 1 , further comprising: forming an uppermost layer of the second semiconductor material of the stack with a sufficient thickness so as to avoid protrusion shape of the S/D structures.
12. 12 . The method of claim 1 , further comprising: forming a protective film over the fin structures; forming a dummy gate over the protective film; and patterning the dummy gate while the protective film protects the fin structures.
13. 13 . The method of claim 12 , further comprising: removing the dummy gate and the protective film to uncover the fin structures in gate regions; and removing the second semiconductor material in the gate regions.
14. 14 . The method of claim 13 , further comprising: forming gate structures all around the channel structures.
15. 15 . The method of claim 12 , wherein: the dummy gate is patterned in a direction orthogonal to the fin structures.
16. 16 . The method of claim 12 , further comprising: forming a hardmask material over the dummy gate.
17. 17 . The method of claim 1 , further comprising: removing the sidewall constraints after forming the S/D structures.
18. 18 . A method of manufacturing a semiconductor device, the method comprising: forming a stack of epitaxially grown lavers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material; forming fin structures from the stack, the fin structures including channel structures formed of the first semiconductor material, the channel structures having opposing ends that are uncovered; forming sidewall constraints at the opposing ends of the channel structures, each pair of the sidewall constraints laterally bounding a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region; forming S/D structures on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints; bonding a first wafer to a second wafer via a first bonding dielectric layer, the first wafer including a first bulk semiconductor material, the second wafer including the stack formed over a second bulk semiconductor material; and removing the second bulk semiconductor material to uncover the stack before forming the fin structures from the stack.
19. 19 . The method of claim 18 , further comprising: removing the first bulk semiconductor material to uncover the first bonding dielectric layer; and forming a power delivery network in contact with the first bonding dielectric layer, the power delivery network including backside power rails in contact with vias that extend through the first bonding dielectric layer.
20. 20 . The method of claim 19 , further comprising: bonding a third wafer to the second wafer via a second bonding dielectric layer, the third wafer including another stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material; removing the third bulk semiconductor material; and forming a tier of transistors from the another stack.

Description

INCORPORATION BY REFERENCE This present disclosure claims the benefit of U.S. Provisional Application No. 63/344,146, filed on May 20, 2022, which is incorporated herein by reference in its entirety. Aspects of the present disclosure are related to Applicant's U.S. Pat. Nos. 10,586,765 and 10,770,479 and Applicant's patent applications titled “Method to Form Silicon-Germanium Nanosheet Structures” (Ser. No. 18/319,857), “Method for Wrap-Around Contact Formation Through the Incorporation of Cladding of an Etch-Selective Semiconductor Material” (Ser. No. 18/319,881), “Sequential Complimentary FET Incorporating Backside Power Distribution Network Through Wafer Bonding Prior to Formation of Active Devices” (Ser. No. 18/319,823), and “Method to Reduce Parasitic Resistance for CFET Devices Through Single Damascene Processing of Vias” (Ser. No. 18/319,915), all of which are incorporated herein by reference in their entirety. FIELD OF THE INVENTION This disclosure relates to microelectronic devices including semiconductor devices, transistors, and integrated circuits, and methods of microfabrication. BACKGROUND In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other. SUMMARY The present disclosure relates to a semiconductor device and a method of forming the semiconductor device. According to a first aspect of the disclosure, a method of manufacturing a semiconductor device is provided. The method includes bonding a first wafer to a second wafer via a first bonding dielectric layer. The first wafer includes a first bulk semiconductor material. The second wafer includes a first stack of alternating layers of epitaxially grown semiconductor layers formed over a second bulk semiconductor material. The second bulk semiconductor material is removed to uncover the first stack. A first tier of transistors is formed from the first stack. A third wafer is bonded to the second wafer via a second bonding dielectric layer. The third wafer includes a second stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material. The third bulk semiconductor material is removed. A second tier of transistors is formed from the second stack. The first bulk semiconductor material is removed to uncover the first bonding dielectric layer. A power delivery network in contact with the first bonding dielectric layer is formed. The power delivery network includes backside power rails in contact with vias that extend through the first bonding dielectric layer. In some embodiments, the backside power rails are formed after forming the first tier of transistors and the second tier of transistors. In some embodiments, before the third wafer is bonded to the second wafer, local interconnect (LI) structures connected to source/drain (S/D) structures of the first tier of transistors are formed. At least one via is formed that connects to a respective LI structure and extends through the first bonding dielectric layer. In some embodiments, a respective backside power rail in contact with the at least one via is formed. In some embodiments, at least one via opening is formed to uncover the first bulk semiconductor material. The at least one via opening is partially filled with a filler material. LI openings are formed, which include a respective LI opening that connects to the at least one via opening. The filler material is removed. The LI openings and the at least one via opening are filled with a conductive material to form the LI structures and the at least one via. In some embodiments, after the third wafer is bonded to the second wafer, LI structures connected to S/D structures of the second tier of transistors are formed. At least one via is formed that connects to a respective LI structure and extends through the second bonding dielectric layer and the first bonding dielectric layer. In some embodiments, a respective backside power rail in contact with the at least one via is formed. In some embodiments, at least one via opening is formed to uncover the first bulk semiconductor material. The at