US-12628412-B2 - Semiconductor device

US12628412B2US 12628412 B2US12628412 B2US 12628412B2US-12628412-B2

Abstract

A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

Inventors

Teruyuki Ohashi
Hiroshi Kono
Masaru Furukawa

Assignees

KABUSHIKI KAISHA TOSHIBA
TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Dates

Publication Date: 20260512
Application Date: 20220922
Priority Date: 20180915

Claims (11)

1 . A semiconductor device comprising: a silicon carbide layer having a first surface and a second surface opposite to the first surface; a first electrode provided on a side of the first surface of the silicon carbide layer; a second electrode provided on a side of the second surface of the silicon carbide layer; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and having a first portion in contact with the first surface; a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface and separated from the second silicon carbide region; a fourth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface and in contact with the first electrode; a fifth silicon carbide region of the first conductivity type provided between the first silicon carbide region and the second silicon carbide region, a first conductivity type impurity concentration of the fifth silicon carbide region being higher than a first conductivity type impurity concentration of the first silicon carbide region; a sixth silicon carbide region of the first conductivity type provided between the first silicon carbide region and the third silicon carbide region, a first conductivity type impurity concentration of the sixth silicon carbide region being higher than the first conductivity type impurity concentration of the first silicon carbide region; a seventh silicon carbide region of the first conductivity type provided between the fifth silicon carbide region and the sixth silicon carbide region, a first conductivity type impurity concentration of the seventh silicon carbide region being lower than the first conductivity type impurity concentration of the fifth silicon carbide region and the first conductivity type impurity concentration of the sixth silicon carbide region, the seventh silicon carbide region provided between the first silicon carbide region and the first surface and being in contact with the first electrode; an eighth silicon carbide region of a second conductivity type provided between the second silicon carbide region and the first surface, a second conductivity type impurity concentration of the eighth silicon carbide region being higher than a second conductivity type impurity concentration of the second silicon carbide region, and the eighth silicon carbide region being in contact with the first electrode; a ninth silicon carbide region of a second conductivity type provided between the third silicon carbide region and the first surface, a second conductivity type impurity concentration of the ninth silicon carbide region being higher than a second conductivity type impurity concentration of the third silicon carbide region, and the ninth silicon carbide region being in contact with the first electrode; a gate electrode provided on a side of the first surface of the silicon carbide layer and facing the first portion of the second silicon carbide region, the gate electrode extending in a first direction parallel to the first surface; and a gate insulating layer provided between the gate electrode and the first portion, wherein a distance between the fifth silicon carbide region and the sixth silicon carbide region is smaller than a distance between the eighth silicon carbide region and the ninth silicon carbide region, wherein a distance between the second surface and the gate electrode is larger than a distance between the second surface and the second silicon carbide region, wherein the second silicon carbide region has a second portion in contact with the first electrode, and wherein an interface between the second portion and the first electrode is located between the first electrode and the fifth silicon carbide region in a vertical direction from the first electrode to the second electrode.
2 . The semiconductor device according to claim 1 , wherein the fifth silicon carbide region is located between an end portion of the second silicon carbide region and the first silicon carbide region, the end portion facing the third silicon carbide region.
3 . The semiconductor device according to claim 1 , further comprising: a tenth silicon carbide region of the first conductivity type provided between the first silicon carbide region and the gate electrode, the tenth silicon carbide region located in a same plane with the fifth silicon carbide region, the same plane being parallel to the first surface, and the tenth silicon carbide region having a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the fifth silicon carbide region.
4 . The semiconductor device according to claim 3 , wherein the tenth silicon carbide region is located between the first portion and the first silicon carbide region.
5 . The semiconductor device according to claim 3 , wherein the tenth silicon carbide region is located between a portion where the fourth silicon carbide region is in contact with the first electrode and the first silicon carbide region.
6 . The semiconductor device according to claim 1 , wherein the first conductivity type impurity concentration of the seventh silicon carbide region is 5% or more and 80% or less of the first conductivity type impurity concentration of the fifth silicon carbide region.
7 . The semiconductor device according to claim 1 , wherein the first conductivity type impurity concentration of the first silicon carbide region is 4×10 14 cm −3 or more and 1×10 17 cm −3 or less.
8 . The semiconductor device according to claim 1 , wherein the first conductivity type impurity concentration of the fifth silicon carbide region is 5×10 16 cm −3 or more and 2×10 17 cm −3 or less.
9 . The semiconductor device according to claim 1 , wherein the first conductivity type impurity concentration of the seventh silicon carbide region is 1×10 16 cm −3 or more and 2×10 17 cm −3 or less.
10 . The semiconductor device according to claim 1 , wherein the fifth silicon carbide region, the sixth silicon carbide region, and the seventh silicon carbide region extend in the first direction.
11 . The semiconductor device according to claim 1 , wherein the first conductivity type impurity concentration of the seventh silicon carbide region is higher than the first conductivity type impurity concentration of the first silicon carbide region.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. application Ser. No. 16/273,414 filed Feb. 12, 2019 and is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-173141, filed on Sep. 15, 2018, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor device. BACKGROUND A silicon carbide is expected as a material for next generation semiconductor devices. In comparison with silicon, the silicon carbide has superior physical properties such as a band gap of about 3 times, a breakdown field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing these characteristics, for example, it is possible to realize a metal oxide semiconductor field effect transistor (MOSFET) with a high breakdown voltage and a low loss, and can be operate at a high temperature. A vertical type MOSFET using silicon carbide includes a pn junction diode as a body diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is turned off, by using the body diode, it becomes possible to allow the reflux current to flow. However, when a reflux current is allowed to flow by using a body diode, stacking faults grow in the silicon carbide layer due to the recombination energy of carriers, and thus, there is a concern that the on-resistance of the MOSFET may increase. An increase in the on-resistance of the MOSFET causes degradation in the reliability of the MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; FIG. 2 is a schematic top view of the semiconductor device according to the first embodiment; FIG. 3 is a schematic top view of the semiconductor device according to the first embodiment; FIG. 4 is a schematic cross-sectional view in the process of manufacturing the semiconductor device according to the first embodiment; FIG. 5 is a schematic cross-sectional view in the process of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a schematic cross-sectional view in the process of manufacturing the semiconductor device according to the first embodiment; FIG. 7 is a schematic cross-sectional view in the process of manufacturing the semiconductor device according to the first embodiment; FIG. 8 is an equivalent circuit diagram of the semiconductor device according to the first embodiment; FIG. 9 is an explanatory diagram of functions and effects of the semiconductor device according to the first embodiment; FIG. 10 is an explanatory diagram of the functions and effects of the semiconductor device according to the first embodiment; FIGS. 11A and 11B are explanatory diagrams of the functions and effects of the semiconductor device according to the first embodiment; FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a second embodiment; FIG. 13 is a schematic cross-sectional view in the process of manufacturing the semiconductor device according to the second embodiment; FIG. 14 is a schematic cross-sectional view in the process of manufacturing the semiconductor device according to the second embodiment; and FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION Hereinafter, embodiments of the invention will be described with reference to the drawings. In addition, the following description, the same or similar members or the like are denoted by the same reference numerals, and the description of the members or the like once described may be omitted as appropriate. In addition, in the following description, the notations n+, n, n−, p+, p, and p− indicate relative magnitude of impurity concentration in respective conductivity types. That is, n+ indicates that the n-type impurity concentration is relatively higher than that of n, and n− indicates that the n-type impurity concentration is relatively lower than that of n. In addition, p+ indicates that the p-type impurity concentration is relatively higher than that of p, and p− indicates that the p-type impurity concentration is relatively lower than that of p. In addition, sometimes, the n+-type and the n−-type may be simply described as n-type, and the p+-type and the p−-type may be simply described as the p-type. The impurity concentration can be measured by secondary ion mass spectrometry (SIMS), for example. In addition, a relative magnitude of an impurity concentration may also be determined from a magnitude of a carrier concentration obtained by, for example, scanning capacitance microscope (SCM). It is considered that the relative magnitude of an impurity concentration is coincides with determined from a relative magnitude of a carrier concentration obtained by SCM. In addition, a distance such as a depth and a thickness of an