US-12628413-B2 - Semiconductor device

US12628413B2US 12628413 B2US12628413 B2US 12628413B2US-12628413-B2

Abstract

A semiconductor device includes an epitaxial layer disposed on a substrate, which both have a first conductivity type. A first well region having a second conductivity type is disposed in the epitaxial layer. A gate is disposed on the first well region. A source contact region and a drain contact region both having the first conductivity type are disposed in the first well region. A second well region having the first conductivity type is disposed in the epitaxial layer, laterally abuts the first well region and is in contact with a portion of the substrate. The second well region and the portion of the substrate constitute a resistor that is electrically coupled to a ground terminal. A heavily doped region having the first conductivity type is disposed in the second well region and electrically connected to the source contact region.

Inventors

Yu-Hao Ho
Cheng-Tsung WU

Assignees

VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

Dates

Publication Date: 20260512
Application Date: 20231114

Claims (15)

1 . A semiconductor device, comprising: a substrate, having a first conductivity type; an epitaxial layer, having the first conductivity type and disposed on the substrate; a first well region, having a second conductivity type and disposed in the epitaxial layer; a gate, disposed on the first well region; a source contact region and a drain contact region, both having the first conductivity type, disposed in the first well region and located on two sides of the gate, respectively; a second well region, having the first conductivity type, disposed in the epitaxial layer, laterally abutting the first well region and in contact with a portion of the substrate, wherein the second well region and the portion of the substrate constitute a resistor, and the resistor is electrically coupled to a ground terminal; and a heavily doped region, having the first conductivity type, disposed in the second well region and electrically connected to the source contact region.
2 . The semiconductor device of claim 1 , further comprising a third well region having the second conductivity type, disposed in the epitaxial layer and surrounding the first well region and the second well region.
3 . The semiconductor device of claim 2 , wherein a portion of the epitaxial layer is located between the second well region and the third well region, and the portion of the epitaxial layer is located directly above the portion of the substrate.
4 . The semiconductor device of claim 3 , wherein the second well region laterally abuts and is in contact with the portion of the epitaxial layer.
5 . The semiconductor device of claim 3 , further comprising a conductive layer disposed directly above the portion of the epitaxial layer, wherein the conductive layer is electrically coupled to the heavily doped region and the source contact region.
6 . The semiconductor device of claim 2 , wherein the second well region laterally abuts and is in contact with the third well region.
7 . The semiconductor device of claim 2 , further comprising a fourth well region having the second conductivity type and disposed in the substrate, wherein the first well region, the second well region and the third well region are all located directly above the fourth well region, and the fourth well region surrounds the portion of the substrate.
8 . The semiconductor device of claim 7 , wherein a bottom surface of the first well region and a bottom surface of the second well region are both in direct contact with a top surface of the fourth well region.
9 . The semiconductor device of claim 7 , wherein a bottom surface of the first well region and a bottom surface of the second well region are both separated from a top surface of the fourth well region by a distance.
10 . The semiconductor device of claim 1 , further comprising a first doped region and a second doped region, both having the first conductivity type and disposed in the first well region, wherein the source contact region and the drain contact region are located in the first doped region and the second doped region, respectively.
11 . The semiconductor device of claim 10 , further comprising a bulk contact region having the second conductivity type, disposed in the first well region, and laterally separated from both the source contact region and the first doped region.
12 . The semiconductor device of claim 1 , wherein the first well region, the source contact region, the drain contact region and the gate constitute a P-type enhancement-mode transistor, the resistor is a P-type resistor, and the P-type enhancement-mode transistor and the P-type resistor are connected in series.
13 . The semiconductor device of claim 12 , wherein the P-type enhancement-mode transistor and the P-type resistor are configured in a high-side drive circuit of a switching circuit to detect a high-side potential signal between a high-side transistor and a low-side transistor.
14 . The semiconductor device of claim 13 , wherein the high-side drive circuit controls the high-side transistor to be turned off according to the high-side potential signal to be detected.
15 . The semiconductor device of claim 13 , wherein a structure of the high-side drive circuit includes an isolation ring, and the second well region is a portion of the isolation ring.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates generally to semiconductor devices in a switch circuit, and more particularly to semiconductor devices including a transistor and a resistor connected in series in a high-side drive circuit. 2. Description of the Prior Art Metal-oxide-semiconductor field-effect-transistors (MOSFETs) are common components used in integrated circuits, and usually used as power switches in various power applications and power supply lines. For example, in a switch circuit (or referred to as a bridge circuit) where switching components are connected in series, MOSFETS are used as switching components and disposed at a high-side circuit and a low-side circuit respectively. The high-side switching component and the low-side switching component are turned on and turned off alternately. In order to prevent the high-side switching component and the low-side switching component from being turned on at the same time to cause a short through circuit, it is usually necessary to provide an additional level shifter to detect the potential signal of the high-side circuit, and then this potential signal is transmitted back to the low-side circuit. When the potential signal of the high-side circuit is detected to have a malfunction, the low-side circuit transmits a signal to shut down the high-side circuit. The additional level shifter is required to be disposed in the current switch circuit. Therefore, the manufacturing cost of the integrated circuit and the size of the chip cannot be effectively reduced. SUMMARY OF THE INVENTION In view of this, the present disclosure provides semiconductor device that includes a transistor and a resistor connected in series in a high-side drive circuit to accurately detect a high-side potential signal between a high-side switching component and a low-side switching component. The semiconductor device prevents the high-side switching component and the low-side switching component from being turned on at the same time to cause a short through circuit. Moreover, the transistor and the resistor are formed by using the structure of the high-side drive circuit without increasing in the footprint of the semiconductor device. Therefore, it is conducive to reduce the manufacturing cost and the size of a chip. According to an embodiment of the present disclosure, a semiconductor device is provided and includes a substrate, an epitaxial layer, a first well region, a gate, a source contact region, a drain contact region, a second well region and a heavily doped region. The substrate has a first conductivity type. The epitaxial layer has the first conductivity type and is disposed on the substrate. The first well region has a second conductivity type and is disposed in the epitaxial layer. The gate is disposed on the first well region. The source contact region and the drain contact region both have the first conductivity type, are disposed in the first well region and located on two sides of the gate respectively. The second well region has the first conductivity type, is disposed in the epitaxial layer, laterally abuts the first well region and is in contact with a portion of the substrate. The second well region and the portion of the substrate constitute a resistor, and the resistor is electrically coupled to a ground terminal. The heavily doped region has the first conductivity type, is disposed in the second well region and electrically connected to the source contact region. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a block diagram of a portion of a switch circuit according to an embodiment of the present disclosure. FIG. 2 is a block diagram of a switch circuit according to an embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to further another embodiment of the present disclosure. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 7, FIG. 8 and FIG. 9 are schematic cross-sectional views of some stages of a method of fabr