US-12628416-B2 - Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, a plurality of active structures, a trench, a lower epitaxy, an upper epitaxy and a bottom barrier portion. The active structures are formed on the substrate and arranged in a first direction. The trench passes through adjacent two of the active structures in a second direction and has a bottom recess. The lower epitaxy is formed on a lower portion of the trench. The upper epitaxy is formed on an upper portion of the trench and separated from the lower epitaxy. The bottom barrier portion is formed on the bottom recess and separates the substrate and the lower epitaxy.

Inventors

• HUNG-YU YEN
• Keng-Chu Lin

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20230419

Claims (20)

1. 1 . A manufacturing method for a semiconductor device, comprising: forming a fin structure on a substrate, wherein the fin structure extends in a first direction; forming a trench passing through the fin structure to form a plurality of active structures, wherein the trench extends, in a second direction and has a bottom recess; forming a bottom barrier portion formed on the bottom recess of the trench; forming a lower epitaxy on a lower portion of the trench; forming a CESL (contact etching stop layer) portion and a ILD (interlayer dielectric) portion within the trench; and forming an upper epitaxy on an upper portion of the trench, wherein the upper epitaxy is separated from the lower epitaxy; wherein in forming the CESL portion and the ILD portion within the trench, the manufacturing method further comprises: forming a CESL material in the trench; forming a ILD material on the CESL material, wherein the CESL material covers a bottom surface of the ILD material and a lateral surface of the ILD material; in the same process, removing a portion of the CESL material and a portion of the ILD material, wherein a remaining portion of the CESL material forms the CESL portion and a remaining portion of the ILD material forms the ILD portion.
2. 2 . The manufacturing method as claimed in claim 1 , further comprising: forming a barrier layer material on a lateral surface of the trench and a sidewall of the bottom recess; and densifying a portion of the barrier layer material to form a barrier layer; wherein the barrier layer has a density greater than that of the barrier layer material.
3. 3 . The manufacturing method as claimed in claim 2 , wherein each active structure comprises an upper active region, a lower active region and a middle spacer separating the upper active region from the lower active region; the barrier layer comprises: the bottom barrier portion located below the middle spacer; and an upper barrier portion located above the middle spacer.
4. 4 . The manufacturing method as claimed in claim 3 , wherein another portion of the barrier layer material is remained to form a remained barrier portion, and the remained barrier portion is located between the bottom barrier portion and the upper barrier portion.
5. 5 . The manufacturing method as claimed in claim 4 , further comprising: removing the remained barrier portion to expose the lower active region; and forming the lower epitaxy on the lower portion of the trench corresponding to the lower active region.
6. 6 . The manufacturing method as claimed in claim 1 , wherein each active structure comprises an upper active region, a lower active region and a middle spacer separating the upper active region from the lower active region; the manufacturing method further comprises: removing the middle spacer to form a hollow portion; and forming a middle inner spacer within the hollow portion.
7. 7 . The manufacturing method as claimed in claim 3 , wherein the barrier layer comprises: a middle barrier portion formed on a lateral surface of the middle spacer; wherein the middle barrier portion extends from the upper barrier portion toward a lower surface of the middle spacer, but not extends to the lower surface of the middle spacer.
8. 8 . The manufacturing method as claimed in claim 3 , further comprising: removing the upper barrier portion to expose the upper active region; and forming the upper epitaxy on the upper portion of the trench corresponding to the upper active region.
9. 9 . The manufacturing method as claimed in claim 3 wherein the barrier layer comprises: a middle barrier portion formed on a lateral surface of the middle spacer; wherein the middle barrier portion has a bottom surface aligned with au upper surface of the middle spacer.
10. 10 . A manufacturing method for a semiconductor device, comprising: forming a fin structure on a substrate, wherein the fin structure extends in a first direction; forming a trench passing through the fin structure to form a plurality of active structures, wherein the trench extends, in a second direction; forming a lower epitaxy on a lower portion of the trench; forming a CESL portion and a ILD portion within the trench; and forming an upper epitaxy on an upper portion of the trench, wherein the upper epitaxy is separated from the lower epitaxy by the CESL portion and the ILD portion; wherein in forming the CESL portion and the ILD portion within the trench, the manufacturing method further comprises: forming a CESL material in the trench; forming a ILD material on the CESL material, wherein the CESL material covers a bottom surface of the ILD material and a lateral surface of the ILD material; in the same process, removing a portion of the CESL material and a portion of the ILD material, wherein a remaining portion of the CESL material forms the CESL portion and a remaining portion of the ILD material forms the ILD portion.
11. 11 . The manufacturing method as claimed in claim 10 , further comprises: before forming the lower epitaxy on the lower portion of the trench, forming a middle barrier portion within the trench.
12. 12 . The manufacturing method as claimed in claim 11 , wherein in forming the middle barrier portion within the trench, the middle barrier portion is formed on a lateral surface of the CESL portion.
13. 13 . The manufacturing method as claimed in claim 10 , further comprising: before forming the lower epitaxy on the lower portion of the trench, forming a bottom barrier portion in the trench.
14. 14 . The manufacturing method as claimed in claim 13 , wherein in forming the trench passing through the fin structure to form the plurality of active structure, the trench has a bottom recess; the manufacturing method further comprises: before forming the lower epitaxy on the lower portion of the trench, forming the bottom barrier portion in the bottom recess of the trench.
15. 15 . The manufacturing method as claimed in claim 13 , wherein the bottom barrier portion and the middle barrier portion are formed of the same material.
16. 16 . A manufacturing method for a semiconductor device, comprising: forming a fin structure on a substrate, wherein the fin structure extends in a first direction; forming a trench passing through the fin structure to form a plurality of active structures, wherein the trench extends, in a second direction; forming a lower epitaxy on a lower portion of the trench; forming a CESL material in the trench; forming a ILD material in the trench; in the same process, removing a portion of the CESL material to form a CESL portion and removing a portion of the ILD material to form an ILD portion; forming an upper epitaxy on an upper portion of the trench, wherein the upper epitaxy is separated from the lower epitaxy by the CESL portion and the ILD portion.
17. 17 . The manufacturing method as claimed in claim 16 , further comprising: before forming the CESL material in the trench, forming an upper barrier portion in the trench.
18. 18 . The manufacturing method as claimed in claim 16 , further comprising: forming a middle barrier portion; and forming a middle inner spacer in the active structure, wherein the middle inner spacer has a lower surface; wherein the middle barrier portion extends toward the lower surface of the middle inner spacer, but not to the lower surface of the middle inner spacer.
19. 19 . The manufacturing method as claimed in claim 16 , further comprising: before forming the lower epitaxy on the lower portion of the trench, forming a bottom barrier portion in the trench.
20. 20 . The manufacturing method as claimed in claim 19 , wherein the bottom barrier portion and a middle barrier portion are formed of the same material.

Description

BACKGROUND For device scaling, to narrow a distance between NMOS and PMOS is the key. NMOS and PMOS are vertically stacked is one of approach to make it. However, the integration flow is challenging. Especially, to pattern the NMOS/PMOS epitaxy in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1_a illustrates a schematic diagram of a cross-sectional view of a semiconductor device 100 in a first direction; FIG. 1_b illustrates a schematic diagram of a cross-sectional view of a semiconductor device 100 in a second direction; FIGS. 2A to 2R_b illustrate schematic diagrams of manufacturing processes of the semiconductor device 100 of FIGS. 1_a and 1_b; FIG. 2D_a illustrates a cross-sectional view of the semiconductor structure of FIG. 2D along a direction 2D_a-2D_a′; FIG. 2D_b illustrates a cross-sectional view of the semiconductor structure of FIG. 2D along a direction 2D_b-2D_b′; FIG. 2E_a illustrates a cross-sectional view of the semiconductor structure of FIG. 2E along a direction 2E_a-2E_a′; FIG. 2E_b illustrates a cross-sectional view of the semiconductor structure of FIG. 2E along a direction 2E_b-2E_b′; FIG. 2F_a illustrates a cross-sectional view of the semiconductor structure of FIG. 2F along a direction 2F_a-2F_a′; FIG. 2F_b illustrates a cross-sectional view of the semiconductor structure of FIG. 2F along a direction 2F_b-2F_b′; FIG. 2G_a illustrates a schematic diagram of densifying the barrier layer material of FIG. 2F_a; FIG. 2G_b illustrates a schematic diagram of densifying the barrier layer material of FIG. 2F_b; FIG. 2H_a illustrates a schematic diagram of removing the remained barrier portion of FIG. 2G_a; FIG. 2H_b illustrates a schematic diagram of removing the remained barrier portion of FIG. 2G_b; FIG. 2I_a illustrates a schematic diagram of removing the middle spacer of FIG. 2H_a; FIG. 2I_b illustrates a schematic diagram of removing the middle spacer of FIG. 2H_b; FIG. 2J_a illustrates a schematic diagram of forming a middle inner spacer within the hollow portion and a lower inner spacer within the lower spacer recess of the lower spacer of FIG. 2I_a; FIG. 2J_b illustrates a schematic diagram of forming the middle inner spacer within the hollow portion and the lower inner spacer within the lower spacer recess of the lower spacer of FIG. 2I_b; FIG. 2K_a illustrates a schematic diagram of forming at least one lower epitaxy within the lower portion of the trench of FIG. 2J_a; FIG. 2K_b illustrates a schematic diagram of forming at least one lower epitaxy within the lower portion of the trench of FIG. 2J_a; FIG. 2L_a illustrates a schematic diagram of forming a contact etching stop layer (CESL) material on the lower epitaxy, the upper barrier portion and the oxide layer of FIG. 2K_a; FIG. 2L_b illustrates a schematic diagram of forming the CESL material on the lower epitaxy, the upper barrier portion and the oxide layer of FIG. 2K_b; FIG. 2M_a illustrates a schematic diagram of removing a portion of the ILD material of FIG. 2L_a; FIG. 2M_b illustrates a schematic diagram of removing a portion of the ILD material of FIG. 2L_b; FIG. 2N_a illustrates a schematic diagram of forming at least one upper inner spacer within the corresponding upper spacer recess of the upper spacers of FIG. 2M_a; FIG. 2N_b illustrates a schematic diagram of forming at least one upper inner spacer within the corresponding upper spacer recess of the upper spacer layers of FIG. 2M_b; FIG. 2O_a illustrates a schematic diagram of forming at least one upper epitaxy within the upper portion of the trench of FIG. 2N_a; FIG. 2O_b illustrates a schematic diagram of forming at least one upper epitaxy within the upper portion of the trench of FIG. 2N_a; FIG. 2P_a illustrates a schematic diagram of forming an upper CESL portion on the upper epitaxy, the middle ILD portion and the poly silicon material of FIG. 2O_a; FIG. 2P_b illustrates a schematic diagram of forming the upper CESL portion on the upper epitaxy, the middle ILD portion and the poly silicon material of FIG. 2O_b; FIG. 2Q_a illustrates a schematic diagram of removing the poly silicon material of FIG. 2P_a; FIG. 2Q_b illustrates a schematic diagram of removing the poly silicon material of FIG. 2P_b; FIG. 2R_a illustrates a schematic diagram of removing the upper spacer of FIG. 2Q_a; and FIG. 2R_b illustrates a schematic diagram of removing the upper spacer of FIG. 2R_b. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are describ