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US-12628417-B2 - Three-dimensional (3D) field effect transistors (FETs) with gate cuts to enhance carrier mobility and related fabrication methods

US12628417B2US 12628417 B2US12628417 B2US 12628417B2US-12628417-B2

Abstract

A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

Inventors

  • Xia Li
  • Ming-Huei Lin
  • Haining Yang

Assignees

  • QUALCOMM INCORPORATED

Dates

Publication Date
20260512
Application Date
20230616

Claims (20)

  1. 1 . A three-dimensional (3D) field-effect transistor (FET) structure, comprising: at least one semiconductor slab, each comprising a channel region configured to conduct a current in a first direction; an insulation layer; a gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the insulation layer and on the at least one semiconductor slab in the channel region; and a gate cut extending through the gate material adjacent to the channel region of the at least one semiconductor slab in the second direction and extending into the insulation layer in a third direction orthogonal to the first direction and the second direction; wherein: the gate cut comprises a gate cut wedge disposed in the insulation layer, the gate cut wedge configured to cause the insulation layer to exert a first force on the channel region of the at least one semiconductor slab in the third direction.
  2. 2 . The 3D FET structure of claim 1 , wherein the gate cut comprises a gate cut wall configured to cause the gate to exert a second force in the second direction.
  3. 3 . The 3D FET structure of claim 2 , wherein: the gate cut wedge comprises a first surface extending in the second direction and the third direction; and the insulation layer is disposed between the first surface and the channel region of the at least one semiconductor slab in the third direction.
  4. 4 . The 3D FET structure of claim 2 , wherein the gate cut wall comprises a first gate cut material configured to cause the second force comprising a compressive force.
  5. 5 . The 3D FET structure of claim 4 , wherein the gate cut wedge comprises a second gate cut material configured to cause the first force comprising a compressive force.
  6. 6 . The 3D FET structure of claim 5 , wherein: the gate cut wall comprises silicon nitride (SiN); and the gate cut wedge comprises SiN.
  7. 7 . The 3D FET structure of claim 4 , wherein the gate cut wedge comprises a second gate cut material configured to cause the first force comprising a tensile force.
  8. 8 . The 3D FET structure of claim 7 , wherein: the gate cut wall comprises silicon nitride (SiN); and the gate cut wedge comprises silicon dioxide (SiO 2 ).
  9. 9 . The 3D FET structure of claim 2 , wherein the gate cut wall comprises a first gate cut material configured to cause the second force comprising a tensile force.
  10. 10 . The 3D FET structure of claim 9 , wherein the gate cut wedge comprises a second gate cut material configured to cause the first force comprising a tensile force.
  11. 11 . The 3D FET structure of claim 10 , wherein: the gate cut wall comprises silicon dioxide (SiO 2 ); and the gate cut wedge comprises SiO 2 .
  12. 12 . The 3D FET structure of claim 9 , wherein the gate cut wedge comprises a second gate cut material configured to cause the first force comprising a compressive force.
  13. 13 . The 3D FET structure of claim 12 , wherein: the gate cut wall comprises silicon dioxide (SiO 2 ); and the gate cut wedge comprises silicon nitride (SiN).
  14. 14 . The 3D FET structure of claim 3 , further comprising: a substrate; wherein the gate cut wedge is disposed in the insulation layer between the gate cut wall and the substrate.
  15. 15 . The 3D FET structure of claim 14 , wherein: the first surface of the gate cut wedge is configured to exert a third force in the second direction.
  16. 16 . The 3D FET structure of claim 15 , wherein the first surface is in contact with the insulation layer between the gate and the substrate.
  17. 17 . The 3D FET structure of claim 1 , wherein the gate material is disposed between the gate cut and the at least one semiconductor slab.
  18. 18 . The 3D FET structure of claim 1 , wherein: the 3D FET structure comprises a fin-type field effect transistor (FinFET); and the at least one semiconductor slab comprises at least one fin.
  19. 19 . The 3D FET structure of claim 1 , wherein: the 3D FET structure comprises a gate-all-around (GAA) field effect transistor (FET); and the at least one semiconductor slab comprises at least one nanosheet.
  20. 20 . The 3D FET structure of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.

Description

BACKGROUND I. Field of the Disclosure The technology of the disclosure relates generally to transistors in integrated circuits and, more particularly, to three-dimensional transistors. II. Background Current flow in channel regions of field-effect transistors (FETs) is controlled by a gate voltage applied to a gate adjacent to the channel region. Where the gate is adjacent to a surface of the channel region, the gate voltage has the effect of opening or shutting a thin conductive channel layer for the flow of majority carriers (i.e., electrons and holes) below the surface. In planar FETs, the conductive channel is formed in one surface of a semiconductor substrate. To increase a total cross-sectional area of the channel region to increase drive strength, fin-type FETs (FinFETs) and gate-all-around (GAA) FETs have been developed. In both FinFETs and GAA FETs, the channel region is induced in multiple faces of a slab of doped semiconductor material. The slab includes two planar faces and two edges between the major faces. The direction current flow is orthogonal to a cross-section of the slab. Being able to apply the gate voltage to both planar surfaces makes it possible to open or shut current channels on both sides of the slab, essentially doubling the drive strength relative to a planar FET. In addition, FinFETs and GAA FETs, which are both three-dimensional (3D) FETs, may include multiple slabs to further increase drive strength. It has been found that applying a force (e.g., stress and strain) to the crystalline structure of the semiconductor slab in the channel region of a FET can improve carrier mobility. However, it can be difficult to apply such stresses to the slabs of 3D FETs. SUMMARY Aspects disclosed in the detailed description include three-dimensional (3D) field-effect transistors (FETs) with gate cuts to enhance carrier mobility. Related methods of fabricating 3D FETs that include gate cuts to enhance carrier mobility are also disclosed. Although the semiconductor slabs (e.g., fins) in fin-type FETs (FinFETs) and the semiconductor slabs (e.g., nanosheets) in gate-all-around (GAA) FETs are oriented along different planes of a crystal structure of a semiconductor wafer, forces applied in the channel regions in the same directions relative to the surfaces of such semiconductor slabs can improve carrier mobility in both types of 3D FETs. In an exemplary 3D FET disclosed herein, a gate cut is provided in a gate adjacent to the channel region to cause a first force in a first direction and a second force in a second direction, orthogonal to the first direction, to be exerted on the channel regions of the semiconductors slabs to improve carrier mobility, thereby increasing drive strength of the 3D FET. The first force and the second force complement each other to enhance the carrier mobility for greater drive strength than can be achieved by either force individually. For example, the gate cut may include a gate cut wall of a first gate cut material to cause the gate to exert the first force on the channel region of the semiconductor slabs in the first direction. In a further example, the gate cut may also include a gate cut wedge to also cause the gate to exert the first force in the first direction and cause the gate to exert the second force in the second direction on the channel region of the semiconductor slabs to further improve carrier mobility. In some examples, the 3D FET may be a P-type FET or an N-type FET, and the 3D FET may be either a FinFET or a GAA FET. In some examples, a 3D complementary metal oxide semiconductor (CMOS) FET may include an NFET and a PFET that each includes a gate cut to improve drive strength. In this regard, in one aspect, a 3D FET structure is disclosed. The 3D FET structure includes at least one semiconductor slab, each comprising a channel region configured to conduct a current in a first direction. The 3D FET structure further includes a gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the at least one semiconductor slab in the channel region, and a gate cut extending through the gate material adjacent to the channel region of the at least one semiconductor slab in the second direction, wherein the gate cut is configured to cause the gate to exert a first force in the second direction and a second force in a third direction orthogonal to the second direction on the channel region of the at least one semiconductor slab. In another aspect, a method of fabricating a 3D FET structure is disclosed. The method includes forming at least one semiconductor slab, each comprising a channel region configured to conduct a current in a first direction. The method further includes forming a gate extending in a second direction orthogonal to the first direction, the gate comprising a gate material disposed on the at least one semiconductor slab in the channel region. The method also includes forming a gate