US-12628418-B2 - Semiconductor device with selectively etched dielectric fins

Abstract

A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

Inventors

• Zhi-Chang Lin
• Wei-Hao Wu
• Jia-Ni YU

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260512

Application Date

20230719

Claims (20)

1. 1 . An Integrated Circuit (IC) device, comprising: a first fin structure that protrudes in a vertical direction, wherein the first fin structure contains a semiconductive material; a second fin structure that protrudes in the vertical direction and that is spaced apart from the first fin structure, wherein the second fin structure contains the semiconductive material; and a third fin structure that protrudes in the vertical direction and located between the first fin structure and the second fin structure in a first horizontal direction, wherein the third fin structure contains a dielectric material, and wherein the third fin structure is shorter than the first fin structure and the second fin structure in the vertical direction, and wherein an uppermost surface of the third fin structure is wider than an uppermost surface of the first fin structure or the second fin structure in the first horizontal direction.
2. 2 . The IC device of claim 1 , wherein the dielectric material of the third fin structure includes silicon oxynitride (SiON), silicon oxy-carbon nitride (SiOCN), silicon oxycarbide (SiOC), hafnium oxide (HfO 2 ) zirconium oxide (ZrO 2 ), or aluminum oxide (AlO x ).
3. 3 . The IC device of claim 1 , further comprising an epi-layer formed over the first fin structure or the second fin structure in the vertical direction; wherein: the first fin structure or the second fin structure has a side surface that extends substantially in the vertical direction; the epi-layer has a side surface that extends in both the vertical direction and the first horizontal direction; and the third fin structure is shorter than the first fin structure or the second fin structure in the vertical direction.
4. 4 . The IC device of claim 3 , further comprising a dielectric spacer located on the side surface of the first fin structure or the second fin structure but not on the side surface of the epi-layer.
5. 5 . The IC device of claim 4 , wherein the third fin structure is spaced apart from the dielectric spacer in the first horizontal direction.
6. 6 . The IC device of claim 3 , further comprising a gate structure that partially wraps around the first fin structure and the second fin structure, wherein the gate structure is disposed adjacent to the epi-layer in a second horizontal direction different from the first horizontal direction.
7. 7 . The IC device of claim 6 , further comprising an isolation layer that partially wraps around the first fin structure, the second fin structure, and the third fin structure, wherein the isolation layer is disposed adjacent to the gate structure in the second horizontal direction.
8. 8 . The IC device of claim 1 , further comprising: a fourth fin structure that protrudes in the vertical direction, wherein the fourth fin structure contains the semiconductive material; a fifth fin structure that protrudes in the vertical direction and that is spaced apart from the fourth fin structure, wherein the fifth fin structure contains the semiconductive material; and a sixth fin structure that protrudes in the vertical direction and located between the fourth fin structure and the fifth fin structure in the first horizontal direction, wherein the sixth fin structure contains the dielectric material, and wherein the sixth fin structure is taller than the third fin structure in the vertical direction.
9. 9 . The IC device of claim 8 , wherein the sixth fin structure is taller than the fourth fin structure and the fifth fin structure.
10. 10 . The IC device of claim 8 , wherein: the first fin structure, the second fin structure, and the third fin structure are located in a first region of the IC device having a first pattern density; and the fourth fin structure, the fifth fin structure, and the sixth fin structure are located in a second region of the IC device having a second pattern density greater than the first pattern density.
11. 11 . The IC device of claim 10 , wherein: the first region of the IC device comprises logic devices or input/output (I/O) devices; and the second region of the IC device comprises static random access memory (SRAM) devices.
12. 12 . The IC device of claim 10 , wherein a number of transistors per unit area in the second region of the IC device is at least twice that of the first region of the IC device.
13. 13 . An Integrated Circuit (IC) device, comprising: a first semiconductive fin structure that protrudes in a vertical direction; a first epi-layer formed over the first semiconductive fin structure in the vertical direction; a second semiconductive fin structure that protrudes in the vertical direction; a second epi-layer formed over the second semiconductive fin structure in the vertical direction; and a dielectric fin structure that protrudes in the vertical direction; wherein: the dielectric fin structure is located between the first semiconductive fin structure and the second semiconductive fin structure in a horizontal direction; an upper surface of the dielectric fin structure is wider than an upper surface of the first semiconductive fin structure or an upper surface of the second semiconductive fin structure in the horizontal direction; and the dielectric fin structure is shorter than the first semiconductive fin structure or the second semiconductive fin structure in the vertical direction.
14. 14 . The IC device of claim 13 , wherein: the first semiconductive fin structure, the first epi-layer, the second semiconductive fin structure, the second epi-layer, and the dielectric fin structure are located in a first region having a first pattern density; the IC device further comprises a second region having a second pattern density that is at least twice as great as the first pattern density, wherein the second region includes: a third semiconductive fin structure that protrudes in the vertical direction; a third epi-layer formed over the third semiconductive fin structure in the vertical direction; a fourth semiconductive fin structure that protrudes in the vertical direction; a fourth epi-layer formed over the fourth semiconductive fin structure in the vertical direction; and a further dielectric fin structure that protrudes in the vertical direction; wherein: the further dielectric fin structure is located between the third semiconductive fin structure and the fourth semiconductive fin structure in the horizontal direction; and the further dielectric fin structure is taller than the dielectric fin structure, the third semiconductive fin structure, and the fourth semiconductive fin structure in the vertical direction.
15. 15 . The IC device of claim 14 , wherein the further dielectric fin structure and the third epi-layer or the fourth epi-layer define an interface that extends substantially in the vertical direction.
16. 16 . The IC device of claim 13 , further comprising dielectric spacers disposed on sidewalls of the first semiconductive fin structure or on sidewalls of the second semiconductive fin structure, wherein the dielectric spacers are free of being in direct physical contact with the dielectric fin structure.
17. 17 . An Integrated Circuit (IC) device, comprising: a first region having a first pattern density, wherein the first region includes: a first source/drain region; a second source/drain region; a first dielectric structure disposed between the first source/drain region and the second source/drain region, wherein the first dielectric structure has a first height; and a first dielectric layer disposed over the first source/drain region, the second source/drain region, and the first dielectric structure; and a second region having a second pattern density greater than the first pattern density, wherein the second region includes: a third source/drain region; a fourth source/drain region; a second dielectric structure disposed between the third source/drain region and the fourth source/drain region, wherein the second dielectric structure has a second height greater than the first height, and wherein an upper surface of the first dielectric structure is wider than an upper surface of the second dielectric structure; and a second dielectric layer disposed over the third source/drain region, the fourth source/drain region, and the second dielectric structure.
18. 18 . The IC device of claim 17 , wherein: the third source/drain region is wider than the first source/drain region or the second source/drain region.
19. 19 . The IC device of claim 17 , wherein: the first dielectric structure is separated from the first source/drain region and the second source/drain region by portions of the first dielectric layer; and the second dielectric structure extends to the third source/drain region or the fourth source/drain region.
20. 20 . The IC device of claim 17 , wherein the first source/drain region and the second source/drain region are portions of a first type of circuit, and wherein the third source/drain region and the fourth source/drain region are portions of a second type of circuit different from the first type.

Description

PRIORITY DATA The present application is a continuation of U.S. patent application Ser. No. 17/568,428 filed on Jan. 4, 2022 entitled “Semiconductor Device And Manufacturing Method Thereof For Selectively Etching Dummy Fins” which is a divisional application of U.S. application Ser. No. 16/279,824, filed Feb. 19, 2019, entitled “Forming Dielectric Dummy Fins With Different Heights In Different Regions Of A Semiconductor Device” issued on Jan. 4, 2022 as U.S. Pat. No. 11,217,585 which claims benefit of U.S. Provisional Patent Application No. 62/736,054, filed on Sep. 25, 2018, each of which are hereby incorporated herein by reference in their respective entireties. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized. Similar developments in IC processing and manufacturing are needed. For example, a three-dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. A FinFET can be thought of as a typical planar device extruded into the gate. A typical FinFET is fabricated with a thin “fin” (or fin structure) extending up from a substrate. The channel of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping around) the channel region of the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from multiple sides. This can be leveraged in a number of ways, and in some applications, FinFETs provide reduced short channel effects, reduced leakage, and higher current flow. In other words, they may be faster, smaller, and more efficient than planar devices. Despite the advantages, existing FinFET devices may still have certain issues. For example, dielectric structures such as dummy fins may be formed to tune an overall fin pattern density, reinforce the mechanical strength of the device fins, and/or enhance the manufacturing capability. However, these dummy fins may also interfere with the lateral growth of source/drain epitaxial layers. As a result, the source/drain epitaxial layers may have smaller sizes, smaller surface areas for silicides, and/or smaller landing window for the conductive contacts to be formed thereon. This may be undesirable in regions of an IC where the spacing between adjacent transistors is relatively large (e.g., in a logic device region). On the other hand, if the dummy fins are vertically shortened so as to not interfere with the lateral growth of the source/drain epitaxial layers, one potential downside is that the source/drain epitaxial layers from adjacent transistors may merge together, if the spacing between adjacent transistors is relatively small (e.g., in a memory device region). Undesirably, this could cause electrical shorting between transistors. Therefore, while existing FinFET devices and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this invention and are therefore not to be considered limiting in scope, for the invention may apply equally well to other embodiments. FIG. 1 is a perspective view of an example FinFET transistor. FIGS. 2-4, 7-8, and 10-13 illustrate three-dimensional perspective views of a semiconductor device at various stages of fabrication according to embodiments of the present disclosure. FIGS. 5-6 and 9 illustrate cross-sectional side views of a semiconductor device at various stages of fabrication according to embodiments of the present disclosure. FIG. 14 is a flowchart illustrating a method of fabricating a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or ex