US-12628419-B2 - Stacked upper transistor and lower transistor

Abstract

A semiconductor device includes one or more lower transistors and includes one or more upper transistors. The upper transistor(s) may be forksheet transistors or cells separated by a forksheet pillar. The upper transistor(s) are stacked vertically above respective lower transistor(s). The device width of the upper transistor(s) is relatively small compared to the device width of the lower transistor. As such, adequate space exists for both a lower source/drain (S/D) contact and an upper S/D contact to exist in a same YY cross sectional plane. The lower S/D contact may bypass the upper transistor and contact the underlying lower S/D region there below.

Inventors

• Ruilong Xie
• Alexander Reznicek
• Daniel Schmidt
• Tsung-Sheng KANG

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260512

Application Date

20230307

Claims (16)

1. 1 . A semiconductor device comprising: a lower transistor and an upper forksheet transistor that share a common gate, the upper forksheet transistor comprising an upper source/drain (S/D) region, the lower transistor comprising a lower S/D region, the upper S/D region located vertically above and inset within a footprint of the lower S/D region, wherein a device width of the upper forksheet transistor is smaller than a device width of the lower transistor, and wherein the upper forksheet transistor comprises a forksheet pillar that separates a first forksheet cell from a second forksheet cell.
2. 2 . The semiconductor device of claim 1 , wherein the lower transistor is a gate all around (GAA) nanosheet transistor.
3. 3 . The semiconductor device according to claim 2 , wherein the lower transistor is a FinFET.
4. 4 . The semiconductor device according to claim 1 , wherein the upper transistor is a nFET.
5. 5 . The semiconductor device according to claim 4 , wherein the lower transistor is a pFET.
6. 6 . The semiconductor device according to claim 1 , wherein the common gate comprises an upper portion connected to one or more upper channels of the upper transistor, a lower portion connected to one or more lower channels of the lower transistor, and a gate column that connects the upper gate portion and the lower gate portion.
7. 7 . The semiconductor device according to claim 6 , wherein the gate column is vertically above the one or more lower channels.
8. 8 . The semiconductor device of claim 7 , wherein the gate column is vertically offset from the one or more upper channels.
9. 9 . The semiconductor device of claim 1 , further comprising a lower S/D region contact that is directly in contact with the lower S/D region, wherein an interlayer dielectric separates the lower S/D region contact from the upper S/D region.
10. 10 . A semiconductor device comprising: a first stacked transistor comprising a first lower FinFET and a first forksheet transistor that share a first common gate, the first forksheet transistor comprising a first upper source/drain (S/D) region, the first FinFET comprising a first lower S/D region, the first upper S/D region located vertically above and inset within a footprint of the first lower S/D region; and a second stacked transistor comprising a second lower FinFET and a second forksheet transistor that share a second common gate, the second forksheet transistor comprising a second upper S/D region, the second lower FinFET comprising a second lower S/D region, the second upper S/D region located vertically above and inset within a footprint of the second lower S/D region, wherein a forksheet pillar separates the first common gate from the second common gate, and wherein a lower gate cut region further separates the first common gate from the second common gate.
11. 11 . The semiconductor device of claim 10 , wherein the forksheet pillar also separates one or more channels of the first forksheet transistor from one or more channels of the second forksheet transistor.
12. 12 . The semiconductor device according to claim 10 , wherein the forksheet pillar also separates the first upper S/D region from the second upper S/D region.
13. 13 . The semiconductor device according to claim 10 , wherein the forksheet pillar is vertically in line with the lower gate cut region.
14. 14 . The semiconductor device according to claim 10 , wherein a bonding layer portion separates the forksheet pillar from the lower gate cut region.
15. 15 . The semiconductor device of claim 14 , further comprising a first lower S/D region contact that is directly in contact with the first lower S/D region, wherein an interlayer dielectric separates the first lower S/D region contact from the first upper S/D region.
16. 16 . A semiconductor device fabrication process comprising: forming a bottom FinFET; bonding forksheet channel layers over the bottom FinFET; forming an upper forksheet transistor from the forksheet channel layers, the upper forksheet transistor comprising a forksheet pillar that separates a first forksheet cell from a second forksheet cell; forming a common gate around channel fins of the bottom FinFET and around channel layers of the first forksheet cell; and forming a gate contact against the common gate, forming a bottom source/drain contact against a bottom source/drain of the bottom FinFET, and forming an upper source/drain contact against an upper source/drain of the first forksheet cell, wherein a device width of the upper forksheet transistor is smaller than a device width of the bottom FinFET.

Description

BACKGROUND The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present disclosure relates to fabrication methods and resulting structures for a stacked transistor that has a vertically stacked upper transistor and lower transistor, for complementary metal oxide semiconductor (CMOS) technologies. In certain semiconductor device fabrication processes, many semiconductor devices, such as n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs), may be fabricated on a single wafer. Non-planar transistor device architectures (e.g., fin-type FETs (FinFETs), gate all around (GAA) FETs, such as nanowire FETs, nanosheet FETs, or the like) can provide increased device density and increased performance over planar transistors. As semiconductor integrated circuits (ICs) and/or chips become smaller, the implementation of stacked FETs has increased. Due to shrinking device sizes, it is difficult to optimize channel mobility characteristics in both a lower FET and an upper FET and/or to place or locate front side contacts to respective gates and source/drain regions of the lower FET and upper FET of the stacked transistor. SUMMARY In an embodiment of the present disclosure, a semiconductor device is presented. The semiconductor device includes a lower transistor and an upper forksheet transistor that share a common gate. The upper forksheet transistor includes an upper source/drain (S/D) region. The lower transistor includes a lower S/D region. The upper S/D region is located vertically above and inset within a footprint of the lower S/D region. A device with of the upper forksheet transistor is smaller than a device width of the lower transistor. The independent formation of the lower transistor and the upper forksheet transistor allows for respective optimized channel mobility therewith, respectively. The relatively smaller device width of the upper forksheet transistor may simplify placement of a front side S/D contact that may bypass the upper forksheet transistor and contact the S/D of the lower transistor. In an example, the lower transistor may be a FinFET or a GAA FET. In an example, the forksheet transistor includes a forksheet pillar. In an example, the upper transistor is a nFET and channel mobility may be optimized by the {100} surface orientation of the forksheet transistor active semiconductor layer channel(s). In an example, the lower transistor is a pFinFET and channel mobility may be optimized by the {110} surface orientation of the FinFET fin channel(s). In an example, the common gate includes an upper portion connected to one or more upper channels of the upper transistor, a lower portion connected to one or more lower channels of the lower transistor, and a gate column that connects the upper gate portion and the lower gate portion. In an example, the gate column is vertically above the one or more lower channels. In an example, the gate column is vertically offset from the one or more upper channels. In an example, the semiconductor device further includes a lower S/D region contact that is directly in contact with the lower S/D region. An interlayer dielectric separates the lower S/D region contact from the upper S/D region. The lower S/D region contact may be placed or located adjacent to or may bypass the upper transistor because of the relatively smaller device width of the upper transistor. In an embodiment of the present disclosure, a semiconductor device is presented. The semiconductor device includes a first stacked transistor and a second stacked transistor. The first stacked transistor includes a first lower FinFET and a first forksheet transistor that share a first common gate. The first forksheet transistor includes a first upper source/drain (S/D) region. The first FinFET includes a first lower S/D region. The first upper S/D region is located vertically above and inset within a footprint of the first lower S/D region. The second stacked transistor includes a second lower FinFET and a second forksheet transistor that share a second common gate, the second forksheet transistor comprising a second upper S/D region, the second lower FinFET comprising a second lower S/D region, the second upper S/D region located vertically above and inset within a footprint of the second lower S/D region. In an example, a forksheet pillar separates first one or more channels of the first forksheet transistor from second one or more channels of the second forksheet transistor. In an example, the forksheet pillar also separates the first upper S/D region from the second upper S/D region. In an example, the forksheet pillar also separates the first common gate from the second common gate. In an example, a lower gate cut region further separates the first common gate from the second common gate. In an example, the forksheet pillar is vertically in line with the lower gate cut region. In an example, a bonding l