US-12628420-B2 - Display substrate and manufacturing method thereof, display device

US12628420B2US 12628420 B2US12628420 B2US 12628420B2US-12628420-B2

Abstract

A display substrate is provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the input circuit includes an input transistor, an active layer of the input transistor is in a strip shape extending along a second direction, and the second direction is different from the first direction.

Inventors

Pengfei Yu
Lu Bai
Jie Dai
Linhong HAN

Assignees

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20250109

Claims (17)

1 . A display substrate, comprising: a base substrate, comprising a display region and a peripheral region located at least a side of the display region, and a shift register unit and a first clock signal line that are on the peripheral region of the base substrate, wherein the first clock signal line extends along a first direction on the base substrate and is connected to a first clock signal terminal to configure to provide a first clock signal to the shift register unit; the shift register unit comprises an input circuit, an output circuit, a first control circuit and an output control circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control a level of a second node in response to a level of the first node and the first clock signal; and the output control circuit is configured to control a level of the output terminal under control of a level of the second node, the output control circuit comprises an output control transistor and a first capacitor, and the output circuit comprises an output transistor and a second capacitor; an active layer of the output control transistor and an active layer of the output transistor are integral and extend along the first direction, the active layer of the output control transistor and the active layer of the output transistor which are integral comprises a first output semiconductor layer and a second output semiconductor layer which are arranged side by side in a second direction different from the first direction, an orthographic projection of the second output semiconductor layer on the base substrate is between an orthographic projection of the first output semiconductor layer on the base substrate and the display region, a gate electrode of the output control transistor and a gate electrode of the output transistor extend along the second direction and are arranged side by side along the first direction, and a side of the orthographic projection of the first output semiconductor layer on the base substrate away from the display region comprises a first sub-notch.
2 . The display substrate according to claim 1 , wherein an electrode where the gate electrode of the output control transistor is located comprises a first horizontal part extending along the first direction, a side of the first horizontal part away from the display region has a first sub-portion, an orthographic projection of the first sub-portion of the first horizontal part on the base substrate is located within an orthographic projection of the first sub-notch on the base substrate.
3 . The display substrate according to claim 2 , wherein the gate electrode of the output control transistor further comprises an inclination part, and the inclination part is connected to a first sub-portion of the first horizontal part.
4 . The base substrate according to claim 3 , wherein the gate electrode of the output control transistor further comprises a second horizontal part, and the second horizontal part and the first horizontal part are connected by the inclination part.
5 . The display substrate according to claim 3 , wherein the inclination part comprises a first side, a range of an included angle between the first side of the inclination part and the first horizontal part is from 110° to 175°, and the first side is located on a side of an orthographic projection of the inclination part on the base substrate close to the orthographic projection of the first output semiconductor layer on the base substrate.
6 . The display substrate according to claim 4 , wherein the inclination part comprises a first side, a range of an included angle between the first side of the inclination part and the first horizontal part is from 5° to 70°, and the first side is located on a side of an orthographic projection of the inclination part on the base substrate close to the orthographic projection of the first output semiconductor layer on the base substrate.
7 . The display substrate according to claim 2 , wherein a side of an orthographic projection of the second output semiconductor layer on the base substrate close to the display region comprises a second sub-notch, and an orthographic projection of a second sub-portion of the first horizontal part on the base substate falls into the second sub-notch.
8 . The display substrate according to claim 2 , wherein an orthographic projection of the first capacitor and an orthographic projection of the second capacitor on the base substrate are located between an orthographic projection of the second output semiconductor layer on the base substrate and the display region, the first capacitor comprises a first electrode and a second electrode, and the first electrode of the first capacitor and the gate electrode of the output control transistor are integral, the second capacitor comprises a first electrode and a second electrode, and the first electrode of the second capacitor and the gate electrode of the output transistor are integral, a side of an orthographic projection of the first electrode of the first capacitor on the base substrate away from the display region comprises a third sub-notch, and a side of an orthographic projection of the first electrode of the second capacitor on the base substrate away from the display region comprises a fourth sub-notch, the third sub-notch and the fourth sub-notch are adjacent along first direction.
9 . The display substrate according to claim 8 , wherein the gate electrode of the control output electrode comprises a plurality of sub-gate electrodes arranged side by side along the first direction, wherein an orthographic projection of at least one of the plurality of sub-gate electrodes on the base substrate is located between the third notch and the fourth notch.
10 . The display substrate according to claim 8 , wherein a shape of the third notch and is complementary to a shape of the fourth notch.
11 . The display substrate according to claim 10 , wherein the third notch comprises a first inclination side, the fourth notch comprises a second inclination side, and the first inclination side and the second inclination side are parallel and opposite to each other, an included angle of the first inclination side and a line where the first horizontal part is located and an included angle of the second inclination side and a line parallel to the first horizontal part are complementary.
12 . The display substrate according to claim 11 , wherein the included angle of the first inclination side and the line where the first horizontal part is located and the included angle of the second inclination side and the line parallel to the first horizontal part are from 30° to 70°.
13 . The display substrate according to claim 1 , wherein a ratio range of a width L 1 of the first notch along the second direction and a width L 2 of the first output semiconductor layer along the second direction is 0.12<L 1 /L 2 <0.30.
14 . The display substrate according to claim 1 , further comprising a column of via holes arranged along the first direction, an orthographic projection of the column of via holes on the base substrate and the orthographic projection of the second capacitor on the base substrate overlap on a side away from the display region.
15 . The display substrate according to claim 1 , wherein, the input circuit comprises an input transistor the shift register unit further comprises a voltage stabilization circuit, the voltage stabilization circuit is connected to the first node and a third node, and is configured to stabilize a level of the third node; and the output circuit is connected to the third node, and is configured to output the output signal to the output terminal under control of the level of the third node, the voltage stabilization circuit comprises a voltage stabilization transistor, the first control circuit comprises a first control transistor and a second control transistor, an active layer of the first control transistor and an active layer of the second control transistor extend along the first direction; an active layer of the input transistor, the active layer of the second control transistor and an active layer of the voltage stabilization circuit are arranged in sequence along the first direction, and an orthographic projection of the active layer of the second control transistor on the base substrate is located between an orthographic projection of the active layer of the input transistor on the base substrate and an orthographic projection of the active layer of the voltage stabilization circuit on the base substrate.
16 . The display substrate according to claim 1 , wherein the shift register unit further comprises a second control circuit, the second control circuit is connected to the first node and the second node and is configured to control the level of the first node under control of the level of the second node and a second clock signal, the second control circuit comprises a first noise reduction transistor and a second noise reduction transistor, wherein an active layer of the first noise reduction transistor and an active layer of the second noise reduction transistor are integral to form a continuous noise reduction semiconductor layer, and the noise reduction semiconductor layer extends along the first direction.
17 . The display substrate according to claim 16 , further comprising a third transfer electrode, wherein third transfer electrode is connected to a first electrode of the first noise reduction transistor and a first electrode of the output control transistor, an orthographic projection of the gate electrode of the output control transistor and an orthographic projection of the third transfer electrode on the base substrate overlap with an orthographic projection of the first notch on the base substrate.

Description

This application is a continuation application of U.S. patent application Ser. No. 18/535,236 filed on Dec. 11, 2023, which is a continuation application of U.S. patent application Ser. No. 17/434,256 filed on Aug. 26, 2021, which is a U.S. National Phase Entry of International Application No. PCT/CN2020/084235 filed Apr. 10, 2020. The above-identified applications are incorporated by reference herein in their entirety. TECHNICAL FIELD At least one embodiment of the present disclosure relates to a display substrate. BACKGROUND In the field of display technology, a pixel array such as a liquid crystal display panel or an Organic Light-emitting Diode, OLED display panel usually includes a plurality of rows of gate lines and a plurality of columns of data lines interlaced with the gate lines. The driving of the gate line can be realized by a bonded integrated driving circuit. In recent years, with the continuous improvement of the preparation technology of amorphous silicon thin film transistors or oxide thin film transistors, the gate driving circuit may be directly integrated on a thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including a plurality of cascaded shift register units may be used to provide switching voltage signals (scanning signals) for the plurality of rows of gate lines of the pixel array, so as to control the plurality of rows of gate lines to be turn on in sequence, and at the same time, data signals are provided to pixel units in corresponding rows in the pixel array by the data lines, so that gray voltages required for displaying various gray scales of an image are formed in each pixel unit, and then a frame of image is displayed. SUMMARY At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a shift register unit and a first clock signal line that are on the base substrate; the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit; the shift register unit comprises an input circuit, an output circuit, a first control circuit and an output control circuit; the input circuit is configured to input an input signal to a first node in response to the first clock signal; the output circuit is configured to output an output signal to an output terminal; the first control circuit is configured to control a level of a second node in response to a level of the first node and the first clock signal; and the output control circuit is configured to control a level of the output terminal under control of a level of the second node; the input circuit comprises an input transistor, an active layer of the input transistor is in a strip shape extending along a second direction, and the second direction is different from the first direction; the input transistor comprises a first gate electrode, a second gate electrode and a connection electrode connecting the first gate electrode and the second gate electrode; and the connection electrode comprises a first part which is connected to the first gate electrode and extends along the first direction, a second part which is connected to the second gate electrode, and a third part which extends along the second direction and is connected to the first part and the second part, and the third part of the connection electrode is connected to the first clock signal line to receive the first clock signal. For example, in the display substrate provided by at least an embodiment of the present disclosure, an included angle between the first direction and the second direction is between 70 degrees and 90 degrees. For example, in the display substrate provided by at least an embodiment of the present disclosure, a first electrode of the input transistor is connected to a signal input electrode through a first connection wire extending along the second direction to receive the input signal. For example, in the display substrate provided by at least an embodiment of the present disclosure, the shift register unit further comprises a wire transfer electrode, the first electrode of the input transistor is electrically connected to a first end of the wire transfer electrode, the wire transfer electrode is in a different layer from the active layer of the input transistor, a second end of the wire transfer electrode is connected to a first end of the first connection wire, the wire transfer electrode is in a different layer from the first connection wire, a second end of the first connection wire is electrically connected to the signal input electrode, and the wire transfer electrode is in a same layer as the signal input electrode. For example, in the display substrate provided by at least an embodiment of the present disclosure, the shift register unit further comprises a first insulation layer, a second insulation layer, and a third insulation lay