US-12628427-B2 - Semiconductor device

US12628427B2US 12628427 B2US12628427 B2US 12628427B2US-12628427-B2

Abstract

A semiconductor device having favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The first semiconductor layer includes a metal oxide. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The second semiconductor layer includes crystalline silicon. The first insulating layer includes a region overlapping with the first transistor with the second insulating layer therebetween. The second insulating layer includes a region overlapping with the second transistor with the first insulating layer therebetween. The second insulating layer has higher film density than the first insulating layer.

Inventors

Yukinori SHIMA
Kenichi Okazaki

Assignees

SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20231107
Priority Date: 20200320

Claims (18)

1 . A semiconductor device comprising: a first semiconductor layer, a second semiconductor layer, a first conductive layer, a second conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first semiconductor layer comprises a metal oxide, wherein the second semiconductor layer comprises crystalline silicon, wherein, in a first region, the second conductive layer and the second semiconductor layer overlap with each other with the fourth insulating layer therebetween, wherein the first insulating layer is positioned over the second semiconductor layer, wherein the second insulating layer is positioned over the first insulating layer, wherein the first semiconductor layer is positioned over the second insulating layer, wherein, in a second region, the first conductive layer and the first semiconductor layer overlap with each other with the third insulating layer therebetween, and wherein the second insulating layer has a lower hydrogen concentration than the first insulating layer.
2 . The semiconductor device according to claim 1 , wherein the hydrogen concentration is obtained by secondary ion mass spectrometry.
3 . The semiconductor device according to claim 1 , wherein, in the second region, the first semiconductor layer includes a channel formation region, and wherein a sheet resistance of the channel formation region is higher than or equal to 1×10 7 Ω/square.
4 . The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises indium and zinc.
5 . The semiconductor device according to claim 1 , wherein, in a third region, the first conductive layer and the first semiconductor layer do not overlap with each other, and wherein, in the third region, the first semiconductor layer comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, helium, neon, argon, krypton, and xenon.
6 . The semiconductor device according to claim 1 , wherein the second insulating layer comprises nitrogen.
7 . A semiconductor device comprising: a first semiconductor layer, a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first semiconductor layer comprises a metal oxide, wherein the second semiconductor layer comprises crystalline silicon, wherein the second conductive layer is positioned over the second semiconductor layer, wherein, in a first region, the second conductive layer and the second semiconductor layer overlap with each other with the fourth insulating layer therebetween, wherein the first semiconductor layer is positioned over the third conductive layer, wherein the third conductive layer and the first semiconductor layer overlap with each other, wherein the first insulating layer is positioned over the second semiconductor layer, wherein the second insulating layer is positioned over the first insulating layer, wherein the first semiconductor layer is positioned over the second insulating layer, wherein, in a second region, the first conductive layer and the first semiconductor layer overlap with each other with the third insulating layer therebetween, and wherein the second insulating layer has a lower hydrogen concentration than the first insulating layer.
8 . The semiconductor device according to claim 7 , wherein the hydrogen concentration is obtained by secondary ion mass spectrometry.
9 . The semiconductor device according to claim 7 , wherein, in the second region, the first semiconductor layer includes a channel formation region, and wherein a sheet resistance of the channel formation region is higher than or equal to 1×10 7 Ω/square.
10 . The semiconductor device according to claim 7 , wherein the first semiconductor layer comprises indium and zinc.
11 . The semiconductor device according to claim 7 , wherein, in a third region, the first conductive layer and the first semiconductor layer do not overlap with each other, and wherein, in the third region, the first semiconductor layer comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, helium, neon, argon, krypton, and xenon.
12 . The semiconductor device according to claim 7 , wherein the second insulating layer comprises nitrogen.
13 . A semiconductor device comprising: a first semiconductor layer, a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, wherein the first semiconductor layer comprises a metal oxide, wherein the second semiconductor layer comprises crystalline silicon, wherein the second conductive layer is positioned over the second semiconductor layer, wherein, in a first region, the second conductive layer and the second semiconductor layer overlap with each other with the fourth insulating layer therebetween, wherein the first semiconductor layer is positioned over the third conductive layer, wherein the third conductive layer and the first semiconductor layer overlap with each other, wherein the first insulating layer is positioned over the second semiconductor layer, wherein the second insulating layer is positioned over the first insulating layer, wherein the first semiconductor layer is positioned over the second insulating layer, wherein, in a second region, the first conductive layer and the first semiconductor layer overlap with each other with the third insulating layer therebetween, wherein the second conductive layer and the third conductive layer are in contact with a top surface of the fourth insulating layer, and wherein the second insulating layer has a lower hydrogen concentration than the first insulating layer.
14 . The semiconductor device according to claim 13 , wherein the hydrogen concentration is obtained by secondary ion mass spectrometry.
15 . The semiconductor device according to claim 13 , wherein, in the second region, the first semiconductor layer includes a channel formation region, and wherein a sheet resistance of the channel formation region is higher than or equal to 1×10 7 Ω/square.
16 . The semiconductor device according to claim 13 , wherein the first semiconductor layer comprises indium and zinc.
17 . The semiconductor device according to claim 13 , wherein, in a third region, the first conductive layer and the first semiconductor layer do not overlap with each other, and wherein, in the third region, the first semiconductor layer comprises at least one of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, helium, neon, argon, krypton, and xenon.
18 . The semiconductor device according to claim 13 , wherein the second insulating layer comprises nitrogen.

Description

This application is a continuation of copending U.S. application Ser. No. 17/911,751, filed on Sep. 15, 2022 which is 371 of international application PCT/IB2021/051895 filed on Mar. 8, 2021 which are all incorporated herein by reference. TECHNICAL FIELD One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment of the present invention relates to a method for manufacturing a semiconductor device or a display device. Note that one embodiment of the present invention is not limited to the above-described technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input/output device, a driving method thereof, and a manufacturing method thereof. A semiconductor device generally means a device that can function by utilizing semiconductor characteristics. BACKGROUND ART As a semiconductor material that can be used in a transistor, an oxide semiconductor using a metal oxide has been attracting attention. For example, Patent Document 1 discloses a semiconductor device in which the field-effect mobility (simply referred to as mobility or μFE in some cases) is increased by stacking a plurality of oxide semiconductor layers, containing indium and gallium in an oxide semiconductor layer serving as a channel in the plurality of oxide semiconductor layers, and making the proportion of indium higher than the proportion of gallium. A metal oxide that can be used for a semiconductor layer can be formed by a sputtering method or the like, and thus can be used for a semiconductor layer of a transistor included in a large display device. In addition, capital investment can be reduced because part of production equipment for a transistor using polycrystalline silicon or amorphous silicon can be retrofitted and utilized. A transistor using a metal oxide has field-effect mobility higher than that in the case of using amorphous silicon; therefore, a high-performance display device provided with driver circuits can be obtained. There is a trend in a display device toward a larger screen, and development taking a screen size of 60 inches diagonal or more or 120 inches diagonal or more into consideration has been progressed. Furthermore, there is a trend in the definition of a screen toward a higher resolution, for example, full high definition (the number of pixels: 1920×1080; also referred to as “2K”, for example), ultra high definition (the number of pixels: 3840×2160; also referred to as “4K”, for example), and super high definition (the number of pixels: 7680×4320; also referred to as “8K”, for example). An increase in screen size or resolution tends to increase wiring resistance in a display portion. Patent Document 2 discloses a technique of forming a low-resistance wiring layer using copper (Cu) in order to suppress an increase in wiring resistance in a liquid crystal display device using an amorphous silicon transistor. REFERENCES Patent Documents [Patent Document 1] Japanese Published Patent Application No. 2014-7399[Patent Document 2] Japanese Published Patent Application No. 2004-163901 SUMMARY OF THE INVENTION Problems to be Solved by the Invention An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a small semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a high-resolution display device. Another object of one embodiment of the present invention is to provide a display device with high operating speed. Another object of one embodiment of the present invention is to provide a highly reliable display device. Another object of one embodiment of the present invention is to provide a display device with a narrow frame. Another object of one embodiment of the present invention is to provide a display device with low power consumption. Another object of one embodiment of the present invention is to provide a novel display device. Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not have to achieve all these objects. Objects other than these can be derived from the description of the specification, the drawings, the claims, and the like. Means for Solving the Proble