US-12628428-B2 - Array of capacitors, an array of memory cells, method used in forming an array of memory cells, methods used in forming an array of capacitors, and methods used in forming a plurality of horizontally-spaced conductive lines

Abstract

A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed.

Inventors

• Marcello Mariani
• Giorgio Servalli

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260512

Application Date

20230801

Claims (5)

1. 1 . An array of capacitors comprising: insulating material directly above conducting material; a plurality of capacitors individually comprising a first capacitor electrode, a second capacitor electrode laterally-outward of the first capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode; and a plurality of conductive lines that are individually longitudinally-elongated horizontally and extend alongside and are directly against the capacitor insulator, individual of the conductive lines comprising the second capacitor electrode of individual of the capacitors, the individual conductive lines comprising a shared of the second capacitor electrodes of immediately-laterally-adjacent of the capacitors and interconnecting the individual second capacitor electrodes longitudinally along the individual conductive lines, the individual conductive lines comprising an upper part that is wider than a lower part in a vertical cross-section laterally through that individual conductive line, the lower part extending through the insulating material and being directly against the conducting material.
2. 2 . The array of claim 1 wherein tops of the wider upper parts are below tops of the first capacitor electrodes.
3. 3 . The array of claim 1 wherein bottoms of the wider upper parts are above bottoms of the first capacitor electrodes.
4. 4 . The array of claim 1 wherein tops of the wider upper parts are below tops of the first capacitor electrodes and bottoms of the wider upper parts are above bottoms of the first capacitor electrodes.
5. 5 . The array of claim 1 wherein the conductive lines are directly electrically coupled together at least in part by the conducting material.

Description

RELATED PATENT DATA This patent resulted from a divisional application of U.S. patent application Ser. No. 17/680,644, filed Feb. 25, 2022, entitled “An Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines”, naming Marcello Mariani and Giorgio Servalli as inventors, which was a divisional application of U.S. patent application Ser. No. 17/107,242, filed Nov. 30, 2020, entitled “An Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines”, naming Marcello Mariani and Giorgio Servalli as inventors, now U.S. Pat. No. 11,355,531, the disclosures of which are incorporated by reference. TECHNICAL FIELD Embodiments disclosed herein pertain to arrays of capacitors, to arrays of memory cells, to methods used in forming an array of memory cells, to methods used in forming an array of capacitors, and to methods used in forming a plurality of horizontally-spaced conductive lines. BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The digitlines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a digitline and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated therefrom by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The gate insulator may be capable of being programmed between at least two retentive capacitive states whereby the transistor is non-volatile. Alternately, the gate insulator may not be so capable whereby the transistor is volatile. Regardless, field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. A capacitor is another type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as a charge may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, in such instances, upon determining the pola