US-12628429-B2 - Deep trench capacitors (DTCs) employing bypass metal trace signal routing, and related integrated circuit (IC) packages and fabrication methods

US12628429B2US 12628429 B2US12628429 B2US 12628429B2US-12628429-B2

Abstract

Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

Inventors

Aniket Patil
Hong Bok We
Joan Rey Villarba BUOT

Assignees

QUALCOMM INCORPORATED

Dates

Publication Date: 20260512
Application Date: 20220801

Claims (20)

1 . A deep trench capacitor (DTC), comprising: a substrate comprising a first surface; a first capacitor disposed in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer; and a metallization layer adjacent to the first surface, the metallization layer comprising: an insulating layer; a first metal contact disposed in the insulating layer and coupled to the first conductive layer; a second metal contact disposed in the insulating layer and coupled to the second conductive layer; a third metal contact disposed in the insulating layer, the third metal contact adjacent to the first surface of the substrate; a fourth metal contact disposed in the insulating layer, the fourth metal contact adjacent to the first surface of the substrate; and a first metal line disposed in the insulating layer, the first metal line coupling the third metal contact to the fourth metal contact; wherein the third metal contact and the fourth metal contact are not electrically coupled to the first capacitor.
2 . The DTC of claim 1 , wherein the metallization layer further comprises: a fifth metal contact disposed in the insulating layer, the fifth metal contact adjacent to the first surface of the substrate; a sixth metal contact disposed in the insulating layer, the sixth metal contact adjacent to the first surface of the substrate; and a second metal line disposed in the insulating layer, the second metal line coupling the fifth metal contact to the sixth metal contact.
3 . The DTC of claim 1 , wherein the metallization layer further comprises: a first contact row comprising the first metal contact and the second metal contact aligned along a first longitudinal axis; and a second contact row comprising a fifth metal contact and a sixth metal contact aligned along a second longitudinal axis parallel to the first longitudinal axis, the fifth metal contact coupled to the first conductive layer and the sixth metal contact coupled to the second conductive layer; the first metal line disposed between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.
4 . The DTC of claim 3 , wherein the metallization layer further comprises: a third contact row comprising a seventh metal contact and an eighth metal contact aligned along a fourth longitudinal axis between the first parallel to the first longitudinal axis and disposed between the first longitudinal axis and the second longitudinal axis, the seventh metal contact coupled to the first conductive layer and the eighth metal contact coupled to the second conductive layer; a ninth metal contact disposed in the insulating layer, the ninth metal contact adjacent to the first surface of the substrate; a tenth metal contact disposed in the insulating layer, the tenth metal contact adjacent to the first surface of the substrate; and a second metal line disposed in the insulating layer, the second metal line coupling the ninth metal contact to the tenth metal contact, the second metal line disposed between the second contact row and the third contact row along a fifth longitudinal axis parallel to the first longitudinal axis.
5 . The DTC of claim 3 , wherein: the third metal contact is disposed in the first contact row; and the fourth metal contact is disposed in the first contact row.
6 . The DTC of claim 3 , wherein: the third metal contact is disposed in the first contact row; and the fourth metal contact is disposed in the second contact row.
7 . The DTC of claim 1 , wherein the metallization layer further comprises: a fifth metal contact disposed in the insulating layer, the fifth metal contact adjacent to the first surface of the substrate; and a second metal line disposed in the insulating layer, the second metal line coupling the third metal contact to the fifth metal contact.
8 . The DTC of claim 1 , wherein the first capacitor is disposed in the substrate between the first surface and a second surface of the substrate opposite the first surface.
9 . The DTC of claim 1 , wherein the first capacitor is disposed in the substrate between the third metal contact and the fourth metal contact.
10 . The DTC of claim 1 , wherein: the first surface of the substrate is disposed in a first plane; a first side of the substrate is disposed in a second plane orthogonal to the first plane; and a second surface of the substrate opposite the first surface is disposed in a third plane parallel to the first plane.
11 . The DTC of claim 1 , further comprising one or more trenches disposed in the substrate, the one or more trenches each comprising an opening in the first surface of the substrate; wherein the first capacitor is disposed in the one or more trenches.
12 . The DTC of claim 1 , further comprising a second capacitor disposed in the substrate, the second capacitor comprising a third conductive layer and a fourth conductive layer; wherein the metallization layer further comprises: a fifth metal contact disposed in the insulating layer and coupled to the third conductive layer; and a sixth metal contact disposed in the insulating layer and coupled to the fourth conductive layer.
13 . The DTC of claim 1 , wherein: the metallization layer comprises a redistribution layer (RDL); and the first metal line comprises a RDL metal line coupling the third metal contact to the fourth metal contact.
14 . The DTC of claim 1 , wherein the metallization layer comprises a solder resist layer, wherein the insulating layer comprises a solder resist material.
15 . The DTC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
16 . A method of fabricating a deep trench capacitor (DTC), comprising: providing a substrate comprising a first surface; forming a first capacitor in the substrate, the first capacitor comprising a first conductive layer and a second conductive layer; and forming a metallization layer adjacent to the first surface of the substrate, comprising: forming an insulating layer; forming a first metal contact disposed in the insulating layer and coupled to the first conductive layer; forming a second metal contact in the insulating layer and coupled to the second conductive layer; forming a third metal contact in the insulating layer and adjacent to the first surface of the substrate; forming a fourth metal contact disposed in the insulating layer and adjacent to the first surface of the substrate; forming a first metal line in the insulating layer coupled to the third metal contact and the fourth metal contact; and not electrically coupling the third metal contact and the fourth metal contact to the first capacitor.
17 . The method of claim 16 , wherein forming the metallization layer further comprises: forming a fifth metal contact in the insulating layer and adjacent to the first surface of the substrate; forming a sixth metal contact in the insulating layer and adjacent to the first surface of the substrate; and forming second metal line in the insulating layer coupled to the fifth metal contact and the sixth metal contact.
18 . The method of claim 16 , wherein the metallization layer further comprises: forming a first contact row in the insulating layer, comprising: forming the first metal contact in the insulating layer coupled to the first metal contact to the first conductive layer; and forming the second metal contact aligned along a first longitudinal axis with the first metal contact in the insulating layer and coupled to the second metal contact to the second conductive layer; forming a second contact row comprising: forming a fifth metal contact in the insulating layer coupled to the first conductive layer; and forming a sixth metal contact in the insulating layer aligned along a second longitudinal axis with the first metal contact and coupled to the second metal contact to the second conductive layer, the second longitudinal axis parallel to the first longitudinal axis; and forming the first metal line further comprises forming the first metal line between the first contact row and the second contact row along a third longitudinal axis parallel to the first longitudinal axis.
19 . The method of claim 16 , further comprising: forming a metal layer on the first surface of the substrate; forming the insulating layer adjacent to the metal layer; forming a masking layer on the insulating layer; forming openings in the insulating layer to form: a fifth metal contact in the metal layer coupled to the first conductive layer; a sixth metal contact in the metal layer coupled to the second conductive layer; a seventh metal contact in the metal layer adjacent to the first surface of the substrate; and an eighth metal contact in the metal layer to the first surface of the substrate.
20 . The method of claim 19 , wherein: forming the first metal contact further comprises forming the first metal contact in contact with the fifth metal contact; forming the second metal contact further comprises forming the second metal contact in contact with the sixth metal contact; forming the third metal contact further comprises forming the third metal contact in contact with the seventh metal contact; and forming the fourth metal contact further comprises forming the fourth metal contact in contact with the eighth metal contact.

Description

BACKGROUND I. Field of the Disclosure The field of the disclosure relates to integrated circuit (IC) packages that include one or more semiconductor dies supported by a package substrate, and more particularly to coupling of capacitors to a package substrate of an IC package to support signal processing and/or power integrity. II. Background Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in an IC package, also called a “semiconductor package” or “chip package.” The IC package includes one or more semiconductor dice (“dies” or “dice”) that are mounted on and electrically coupled to a package substrate to provide physical support and an electrical interface to the die(s). The die(s) is electrically interfaced to metal interconnects (e.g., metal traces, metal lines) in a top metallization layer of the package substrate. The package substrate can also include one or more other metallization layers that include metal interconnects (e.g., metal traces, metal lines) with vertical interconnect accesses (vias) coupling the metal interconnects together between adjacent metallization layers to provide electrical interfaces through the package substrate to the die(s). The package substrate also includes a bottom, outer metallization layer that includes metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide an external interface between the die(s) in the IC package. The external metal interconnects can also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the IC package to the PCB to interface its die(s) with the other circuitry coupled to the PCB. It is common to include capacitors in IC packages. Capacitors may be coupled to an IC package to provide a decoupling capacitance for circuits in a die to shunt noise from one electrical circuit (e.g., a power supply circuit) to another electrical circuit (e.g., a powered electrical circuit). Capacitors may also be coupled to an IC package as part of a filtering circuit for a die. Such capacitors can be provided as deep trench capacitors (DTCs). A DTC is formed similar to a semiconductor device, and thus has the advantage of being able to be fabricated using semiconductor fabrication methods. An advantage of using DTCs is that DTCs can be placed closer to a circuit in the IC package. A DTC includes vertical semiconductor devices formed in deep trenches in a silicon substrate to form parallel plate capacitors. The capacitors are each formed by an inner electrode as an inner conducive layer that is surrounded by a dielectric material within a given trench. An outer plate as an outer conductive layer is disposed in the trench adjacent to the dielectric material such that a capacitor is formed between the inner electrode and outer plate. A DTC can be coupled to an outer surface of a package substrate that is also coupled to a die in an IC package as a die-side capacitor (DSC). A DTC can also be coupled to an opposite outer surface of a package substrate that the die is disposed on as a land-side capacitor (LSC). A DTC can also be embedded within a package substrate of an IC package. For example, the capacitor may be embedded in a core substrate of a cored package substrate. In each of these examples of DTCs, metal interconnects/metal traces within metallization layers of the package substrate provide an electrical connection between a die and the DTC. SUMMARY OF THE DISCLOSURE Aspects disclosed herein include deep trench capacitors (DTCs) employing bypass metal trace signal routing. Related integrated circuit (IC) packages and fabrication methods are also disclosed. The DTC can be coupled to or embedded in a package substrate of the IC package to provide capacitance to circuits in a semiconductor die (“die”) in the IC package. The DTC is coupled to the die through metal lines in a metallization layer(s) of the package substrate coupling the DTC to the die. In exemplary aspects, the DTC includes a substrate with trenches disposed therein. Capacitors are formed in the trenches with metal contacts (i.e., terminals) of the capacitors disposed adjacent to an outer surface of the substrate. The DTC also includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. The outer metallization layer includes an insulating layer with metal interconnects (e.g., metal pads) disposed therein and coupled to the metal contacts of the capacitors. Metal bumps can be formed in openings in the insulating layer and coupled to the metal interconnects to provide an interface between the metal bumps and the capacitors in the DTC. In exemplary aspects, to make available signal paths that can extend through a DTC, the outer metallization layer of the DTC also includes additional metal interconnects. These additional metal interconnects in the outer metallization layer of the DTC are not coupled to the capacitors in the DT