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US-12628430-B2 - 3D semiconductor device and structure including power distribution grids

US12628430B2US 12628430 B2US12628430 B2US 12628430B2US-12628430-B2

Abstract

A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the first single crystal transistors or second transistors include at least two FinFet transistors each having different threshold voltages.

Inventors

  • Zvi Or-Bach
  • Brian Cronquist
  • Deepak Sekar

Assignees

  • MONOLITHIC 3D INC.

Dates

Publication Date
20260512
Application Date
20250609

Claims (20)

  1. 1 . A 3D device, the device comprising: a first level, said first level comprising a first single crystal layer; control circuitry disposed in and/or on said first level, wherein said control circuitry comprises first single crystal transistors; a first metal layer, a second metal layer, and a third metal layer, wherein said first metal layer, and/or said second metal layer, and/or said third metal layer comprise connections between said first single crystal transistors; at least one second level disposed on top of or above said first level, wherein said at least one second level comprises a plurality of second transistors, and wherein said at least one second level comprises a plurality of memory cells; a fourth metal layer disposed above said at least one second level; a fifth metal layer disposed above said fourth metal layer, wherein said at least one second level comprises at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; and a local power distribution grid, wherein at least one of said plurality of second transistors comprises a metal gate, wherein said first level comprises a plurality of first Electrostatic Discharge (ESD) circuits, and wherein said first single crystal transistors or said second transistors comprise at least two FinFet transistors each having different threshold voltages (Vt).
  2. 2 . The device according to claim 1 , wherein said local power distribution grid comprises said second metal layer.
  3. 3 . The device according to claim 1 , wherein a first typical thickness of said fifth metal layer is at least 50% greater than a second typical thickness of said second metal layer.
  4. 4 . The device according to claim 1 , wherein a second typical thickness of said second metal layer is at least 50% greater than a third typical thickness of said third metal layer.
  5. 5 . The device according to claim 1 , wherein said second level comprises a plurality of structures deposited using Atomic Layer Deposition (“ALD”).
  6. 6 . The device according to claim 1 , further comprising: a third level disposed between said second level and said fourth metal layer, wherein said third level comprises a plurality of third transistors.
  7. 7 . The device according to claim 1 , wherein said second level comprises a plurality of second Electrostatic Discharge (ESD) circuits.
  8. 8 . A 3D device, the device comprising: a first level, said first level comprising a first single crystal layer; control circuitry disposed in and/or on said first level, wherein said control circuitry comprises first single crystal transistors; a first metal layer, a second metal layer, and a third metal layer, wherein said first metal layer, and/or said second metal layer, and/or said third metal layer comprise connections between said first single crystal transistors; at least one second level disposed on top of or above said first level, wherein said at least one second level comprises a plurality of second transistors, and wherein said at least one second level comprises a plurality of memory cells; a fourth metal layer disposed above said at least one second level; a fifth metal layer disposed above said fourth metal layer, wherein said at least one second level comprises at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, wherein at least one of said plurality of second transistors comprises a metal gate; a conductive connection path from said fifth metal layer to said second metal layer, wherein said conductive connection path comprises a via disposed through said second level; and a plurality of capacitors.
  9. 9 . The device according to claim 8 , wherein said local power distribution grid comprises said second metal layer.
  10. 10 . The device according to claim 8 , wherein a first typical thickness of said fifth metal layer is at least 50% greater than a second typical thickness of said second metal layer.
  11. 11 . The device according to claim 8 , wherein a second typical thickness of said second metal layer is at least 50% greater than a third typical thickness of said third metal layer.
  12. 12 . The device according to claim 8 , wherein said first level comprises a plurality of Electrostatic Discharge (ESD) circuits.
  13. 13 . The device according to claim 8 , further comprising: a third level disposed between said second level and said fourth metal layer, wherein said third level comprises a plurality of third transistors.
  14. 14 . The device according to claim 8 , further comprising: a conductive connection path from said fifth metal layer to said second metal layer, wherein said conductive connection path comprises a via disposed through said second level.
  15. 15 . A 3D device, the device comprising: a first level, said first level comprising a first single crystal layer; control circuitry disposed in and/or on said first level, wherein said control circuitry comprises first single crystal transistors; a first metal layer, a second metal layer, and a third metal layer, wherein said first metal layer, and/or said second metal layer, and/or said third metal layer comprise connections between said first single crystal transistors; at least one second level disposed on top of or above said first level, wherein said at least one second level comprises a plurality of second transistors, wherein said at least one second level comprises a plurality of memory cells; a fourth metal layer disposed above said at least one second level; a fifth metal layer disposed above said fourth metal layer, wherein said at least one second level comprises at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, wherein at least one of said plurality of second transistors comprises a metal gate; a conductive connection path from said fifth metal layer to said second metal layer, wherein said conductive connection path comprises a via disposed through said second level; and a plurality of power supply noise reduction capacitors.
  16. 16 . The device according to claim 15 , wherein a first typical thickness of said fifth metal layer is at least 50% greater than a second typical thickness of said second metal layer.
  17. 17 . The device according to claim 15 , wherein a second typical thickness of said second metal layer is at least 50% greater than a third typical thickness of said third metal layer.
  18. 18 . The device according to claim 15 , wherein said second level comprises a plurality of Electrostatic Discharge (ESD) circuits.
  19. 19 . The device according to claim 15 , further comprising: a third level disposed between said second level and said fourth metal layer, wherein said third level comprises a plurality of third transistors.
  20. 20 . The device according to claim 15 , further comprising: a conductive connection path from said fifth metal layer to said second metal layer, wherein said conductive connection path comprises a via disposed through said second level.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Circuit (3D-IC) devices and fabrication methods. 2. Discussion of Background Art Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs. 3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low. There are many techniques to construct 3D stacked integrated circuits or chips including: Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,406,670, 9,460,978, 9,509,313, 9,640,531, 9,691,760, 9,711,407, 9,721,927, 9,799,761, 9,871,034, 9,953,870, 9,953,994, 10,014,292, 10,014,318, 10,515,981, 10,892,016, 10,991,675, 11,121,121, 11,502,095, 10,892,016, 11,270,988; and U.S. Patent Application Publications and applications, Ser. No. 14/642,724, Ser. No. 15/150,395, Ser. No. 15/173,686, 62/651,722; 62/681,249, 62/713,345, 62/770,751, 62/952,222, 62/824,288, 63/075,067, 63/091,307, 63/115,000, 63/220,443, 2021/0242189, 2020/0013791; and PCT Applications (and Publications): PCT/US2010/052093, PCT/US2011/042071 (WO2012/015550), PCT/US2016/52726 (WO2017053329), PCT/US2017/052359 (WO2018/071143), PCT/US2018/016759 (WO2018144957), PCT/US2018/52332 (WO 2019/060798), PCT/US2021/44110, and PCT/US22/44165. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference.Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031, 9,941,319, 10,679,977, 10,943,934, 10,998,374, 11,063,071, and 11,133,344. The entire contents of all of the foregoing patents are incorporated herein by reference. Regardless of the technique used to construct 3D stacked integrated circuits or chips, heat removal is a serious issue for this technology. For example, when a layer of circuits with power density P is stacked atop another layer with power density P, the net power density is 2P. Removing the heat produced due to this power density is a significant challenge. In addition, many heat producing regions in 3D stacked integrated circuits or chips have a high thermal resistance to the heat sink, and this makes heat removal even more difficult. Several solutions have been proposed to tackle this issue of heat removal in 3D stacked integrated circuits and chips. These are described in the following paragraphs. Publications have suggested passing liquid coolant through multiple device layers of a 3D-IC to remove heat. This is described in “Microchannel Cooled 3D Integrated Systems”, Proc. Intl. Interconnect Technology Conference, 2008 by D. C. Sekar, et al., and “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. Intersoc. Conference on Thermal Management (ITHERM), 2008 by T. Brunschweiler, et al. Thermal vias have been suggested as techniques to transfer heat from stacked device layers to the heat sink. Use of power and ground vias for thermal conduction in 3D-ICs has also been suggested. These techniques are described in “Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity” ACM Transactions on Design Automation of Electronic Systems (TODAES), May 2009 by Hao Yu, Joanna Ho