US-12628432-B2 - Semiconductor device

US12628432B2US 12628432 B2US12628432 B2US 12628432B2US-12628432-B2

Abstract

A semiconductor device includes a substrate having first to fourth regions, first to third active regions and a first dummy active region extending on the first to fourth regions, respectively, a first gate structure intersecting the first active region on the first region and including a first gate conductive layer, a second gate structure intersecting the second active region on the second region and including a second gate conductive layer, a third gate structure intersecting the third active region on the third region find including a third gate conductive layer, a first dummy gate structure intersecting the first dummy active region on the fourth region and including a first dummy gate conductive layer, and source/drain regions on the first to third active regions and on both sides of the first to third gate structures.

Inventors

Jinmyoung LEE
HYUNGSOON JANG
Baekyoung KIM
Hyunah ROH
Jongsoo BAEK
Boyoung Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20221024
Priority Date: 20220110

Claims (20)

1 . A semiconductor device comprising: a substrate having first to fourth regions; first to third active regions extending on the first to third regions, respectively; a first dummy active region extending on the fourth region; a first gate structure intersecting the first active region on the first region, the first gate structure including a first gate conductive layer; a second gate structure intersecting the second active region on the second region, the second gate structure including a second gate conductive layer; a third gate structure intersecting the third active region on the third region, the third gate structure including a third gate conductive layer; a first dummy gate structure intersecting the first dummy active region on the fourth region, the first dummy gate structure including a first dummy gate conductive layer to which an electrical signal is not applied; and source/drain regions on the first to third active regions and on both sides of the first to third gate structures, wherein the first dummy gate conductive layer has a thickness that is different from thicknesses of the first to third gate conductive layers, the first to third gate structures are in corresponding ones of a plurality of standard cells, respectively, the first dummy gate conductive layer is in a respective filler cell between a corresponding pair of the plurality of standard cells, and the first dummy gate conductive layer is configured to have different thicknesses depending on a location thereof.
2 . The semiconductor device of claim 1 , wherein the first dummy gate conductive layer includes a same material as a material of the first to third gate conductive layers.
3 . The semiconductor device of claim 2 , wherein the first dummy gate conductive layer and the first to third gate conductive layers include at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or lanthanum oxide (LaO).
4 . The semiconductor device of claim 1 , wherein each of the first dummy gate conductive layer and the first to third gate conductive layers has a uniform thickness.
5 . The semiconductor device of claim 1 , wherein the first gate conductive layer has a first thickness, the second gate conductive layer has a second thickness greater than the first thickness, the third gate conductive layer has a third thickness greater than the second thickness, and the first to third gate structures constitutes transistors having different threshold voltages.
6 . The semiconductor device of claim 5 , wherein the first dummy gate conductive layer has a fourth thickness greater than the third thickness.
7 . The semiconductor device of claim 5 , wherein the first dummy gate conductive layer has a fourth thickness less than the first thickness.
8 . The semiconductor device of claim 5 , wherein the substrate further includes a fifth region, and the semiconductor device further comprises, a second dummy active region extending on the fifth region, and a second dummy gate structure extending to intersect the second dummy active region on the fifth region, the second dummy gate structure having a second dummy gate conductive layer, and the second dummy gate conductive layer has a fifth thickness that is different from a fourth thickness of the first dummy gate conductive layer.
9 . The semiconductor device of claim 8 , wherein the fifth thickness is different from the first to third thicknesses.
10 . The semiconductor device of claim 1 , wherein each of the first to third gate structures includes a gate dielectric layer covering outer and bottom surfaces of the first to third gate conductive layers, a gate capping layer on the first to third gate conductive layers, an upper conductive layer covering inner surfaces of the first to third gate conductive layers, and gate spacer layers on side surfaces of the gate dielectric layer.
11 . The semiconductor device of claim 10 , wherein the first dummy gate structure includes the gate dielectric layer covering outer and bottom surfaces of the first dummy gate conductive layer, the gate capping layer on the first dummy gate conductive layer, the upper conductive layer covering an inner side surface of the first dummy gate conductive layer, and the gate spacer layers on the side surfaces of the gate dielectric layer.
12 . The semiconductor device of claim 1 , further comprising: a plurality of channel layers spaced apart from each other in a vertical direction on the first to third regions, the vertical direction being perpendicular to the substrate, wherein the first to third gate structures intersect corresponding ones of the first to third active regions and corresponding ones of the plurality of channel layers, respectively, and the source/drain regions are in contact with the plurality of channel layers, respectively.
13 . A semiconductor device comprising: a substrate; a plurality of circuit function blocks including a plurality of standard cells and a plurality of filler cells interposed between the plurality of standard cells, the plurality of standard cells spaced apart from each other on the substrate and configured to perform different circuit functions, respectively; and a dummy structure between the plurality of circuit function blocks on the substrate, wherein the plurality of standard cells each include an active region, a gate structure intersecting the active region, and source/drain regions on the active region and on both sides of the gate structure, the plurality filler cells each include a first dummy active region and a first dummy gate structure intersecting the first dummy active region, the dummy structure includes a second dummy active region and a second dummy gate structure, the second dummy gate structure including a dummy gate conductive layer and intersecting the second dummy active region, the gate structure has a structure that is different from at least one of the first dummy gate structure or the second dummy gate structure, the dummy gate conductive layer is in a respective filler cell between a corresponding pair of the plurality of standard cells, and the dummy gate conductive layer is configured to have different thicknesses depending on a location thereof.
14 . The semiconductor device of claim 13 , wherein the gate structure includes a gate conductive layer, the first dummy gate structure includes a first dummy gate conductive layer, the first dummy gate conductive layer including a same material as the gate conductive layer, the second dummy gate structure includes a second dummy gate conductive layer, the second dummy gate conductive layer including a same material as the gate conductive layer, and each of the gate conductive layer and the first and second dummy gate conductive layers has a uniform thickness.
15 . The semiconductor device of claim 14 , wherein a first thickness of the gate conductive layer is different from a second thickness of the first dummy gate conductive layer, and a third thickness of the second dummy gate conductive layer is different from the first thickness and the second thickness.
16 . The semiconductor device of claim 13 , wherein the plurality of standard cells include first to third standard cells, the first to third standard cells including transistors having different threshold voltages, respectively, the first standard cell includes a first gate structure having a first gate conductive layer, the second standard cell includes a second gate structure having a second gate conductive layer, the third standard cell includes a third gate structure having a third gate conductive layer, and the first dummy gate structure includes a first dummy gate conductive layer.
17 . The semiconductor device of claim 16 , wherein the first to third gate conductive layers and the first dummy gate conductive layer have different thicknesses from each other.
18 . The semiconductor device of claim 16 , wherein the first dummy gate conductive layer includes a first material layer and a second material layer including a material different from the first material layer, the first material layer includes a same material as a material of at least one of the first to third gate conductive layers, and the second material layer includes a same material as a material of at least one of the first to third gate conductive layers.
19 . A semiconductor device comprising: a substrate having first to fourth regions; a first gate structure on the first region, the first gate structure including a sequentially stacked structure of a gate dielectric layer, a first gate conductive layer, and an upper conductive layer, a gate capping layer on the upper conductive layer, and gate spacer layers on sidewalls of the gate dielectric layer; a second gate structure on the second region, the second gate structure including a sequentially stacked structure of the gate dielectric layer, a second gate conductive layer, and the upper conductive layer, the gate capping layer on the upper conductive layer, and the gate spacer layers on the sidewalls of the gate dielectric layer; a third gate structure on the third region, the third gate structure including a sequentially stacked structure of the gate dielectric layer, a third gate conductive layer, and the upper conductive layer, the gate capping layer on the upper conductive layer, and the gate spacer layers on the sidewalls of the gate dielectric layer; and a dummy gate structure on the fourth region, the dummy gate structure including a sequentially stacked structure of the gate dielectric layer, a dummy gate conductive layer, and the upper conductive layer, the gate capping layer on the upper conductive layer, and the gate spacer layers on the sidewalls of the gate dielectric layer, wherein the first to third gate conductive layers and the dummy gate conductive layer include a same material, the first to third gate conductive layers and the dummy gate conductive layer have thicknesses different from each other, the first to third gate structures are in corresponding ones of a plurality of standard cells, respectively, the dummy gate conductive layer is in a respective filler cell between a corresponding pair of the plurality of standard cells, and the dummy gate conductive layer is configured to have different thicknesses depending on a location thereof.
20 . The semiconductor device of claim 19 , wherein the substrate includes circuit regions and a dummy region, the circuit regions including the plurality of standard cells that are spaced apart from each other and configured to perform different circuit functions, respectively, the first to third regions are partial regions of the circuit regions, respectively, and the fourth region is a partial region of the dummy region.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)) This application claims benefit of priority to Korean Patent Application No. 10-2022-0003186 filed on Jan. 10, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND The present inventive concepts relate to semiconductor devices. In line with growing demand for high performance, high speed, and/or multifunctionality of semiconductor devices, the degree of integration of semiconductor devices has increased. With the trend for high integration of semiconductor devices, scaling down of transistors in semiconductor devices has been accelerated, and methods for forming transistors capable of providing various operating voltages, while having a reduced size, have been researched. SUMMARY An aspect of the present inventive concepts is to provide semiconductor devices having improved electrical characteristics and production yield. According to an aspect of the present inventive concepts, a semiconductor device includes a substrate having first to fourth regions, a first active region, a second active region, and a third active region extending on the first to third regions, respectively, a first dummy active region extending on the fourth region, a first gate structure intersecting the first active region on the first region and including a first gate conductive layer, a second gate structure intersecting the second active region on the second region and including a second gate conductive layer, a third gate structure intersecting the third active region on the third region and including a third gate conductive layer, a first dummy gate structure intersecting the first dummy active region on the fourth region and including a first dummy gate conductive layer to which an electrical signal is not applied, and source/drain regions on the first to third active regions and on both sides of the first to third gate structures, wherein the first dummy gate conductive layer has a thickness that is different from thicknesses of the first to third gate conductive layers. According to another aspect of the present inventive concepts, a semiconductor device includes a substrate, a plurality of circuit function blocks including a plurality of standard cells and a plurality of filler cells interposed between the plurality of standard cells spaced apart from each other on the substrate and configured to perform different circuit functions, respectively, and a dummy structure between the plurality of circuit function blocks on the substrate, wherein the plurality of standard cells each include an active region, a gate structure intersecting the active region, and source/drain regions on the active region and on both sides of the gate structure, the plurality filler cells each include a first dummy active region and a first dummy gate structure intersecting the first dummy active region, the dummy structure includes a second dummy active region and a second dummy gate structure intersecting the second dummy active region, and the gate structure has a structure that is different from at least one of the first dummy gate structure or the second dummy gate structure. According to another aspect of the present inventive concepts, a semiconductor device includes a substrate having first to fourth regions, a first gate structure on the first region, the first gate structure including a sequentially stacked structure of a gate dielectric layer, a first gate conductive layer, and an upper conductive layer, a gate capping layer on the upper conductive layer, and gate spacer layers on sidewalls of the gate dielectric layer, a second gate structure on the second region, the second gate structure including a sequentially stacked structure of the gate dielectric layer, a second gate conductive layer, and the upper conductive layer, the gate cupping layer on the upper conductive layer, and the gate spacer layers on the sidewalls of the gate dielectric layer, a third gate structure on the third region, the third gate structure including a sequentially stacked structure of the gate dielectric layer, a third gate conductive layer, and the upper conductive layer, the gate capping layer on the upper conductive layer, and the gate spacer layers on the sidewalls of the gate dielectric layer, and a dummy gate structure on the fourth region, the dummy gate structure including a sequentially stacked structure of the gate dielectric layer, a dummy gate conductive layer, and the upper conductive layer, the gate capping layer on the upper conductive layer, and the gate spacer layers on the sidewalls of the gate dielectric layer, wherein the first to third gate conductive layers and the dummy gate conductive layer include a same material, and the first to third gate conductive layers and the dummy gate conductive layer have thicknesses different from each other. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and ad