US-12628433-B2 - Semiconductor structure and method of manufacture

Abstract

A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a first doped well doped with a first impurity having a first conductivity type, a second doped well adjacent the first doped well and doped with a second impurity having a second conductivity type opposite the first conductivity type, a third doped well adjacent the second doped well and doped with a third impurity having the first conductivity type, a fourth doped region in the third doped well and doped with a fourth impurity having the second conductivity type, and a deep doped well doped with a fifth impurity having the first conductivity type under a first portion of the second doped well, under the third doped well, and under the fourth doped region.

Inventors

• HUNG-CHOU LIN
• Yi-Cheng CHIU
• Chen-Chien Chang
• Kang-Tai PENG
• Tian Sheng Lin

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date

20260512

Application Date

20230316

Claims (20)

1. 1 . A semiconductor structure, comprising: a first doped well doped with a first impurity having a first conductivity type; a second doped well adjacent the first doped well and doped with a second impurity having a second conductivity type opposite the first conductivity type; a third doped well adjacent the second doped well and doped with a third impurity having the first conductivity type; a fourth doped region in the third doped well and doped with a fourth impurity having the second conductivity type; a deep doped well doped with a fifth impurity having the first conductivity type under a first portion of the second doped well, under the third doped well, and under the fourth doped region; a buried well doped with a sixth impurity having the second conductivity type under a second portion of the second doped well and under a first portion of the deep doped well; a first blocking layer doped with a seventh impurity having the second conductivity type adjacent the buried well and under the first doped well; and a second blocking layer doped with an eighth impurity having the first conductivity type adjacent the buried well and under a second portion of the deep doped well.
2. 2 . The semiconductor structure of claim 1 , comprising: a semiconductor layer between the second doped well and third doped well.
3. 3 . The semiconductor structure of claim 1 , wherein: the fourth doped region defines a first PN junction with the third doped well and a second PN junction with the deep doped well.
4. 4 . The semiconductor structure of claim 1 , comprising: a fifth doped region adjacent the third doped well and the deep doped well and doped with a seventh impurity having the second conductivity type.
5. 5 . The semiconductor structure of claim 4 , wherein: the fourth doped region defines a first PN junction with the third doped well and a second PN junction with the deep doped well; and the fifth doped region defines a first PN junction with the third doped well and a second PN junction with the deep doped well.
6. 6 . The semiconductor structure of claim 1 , wherein: the fourth doped region extends partially into the third doped well without contacting the deep doped well.
7. 7 . The semiconductor structure of claim 1 , wherein the second portion of the second doped well contacts the buried well.
8. 8 . The semiconductor structure of claim 1 , wherein the second portion of the second doped well is laterally between a sidewall of the deep doped well and a sidewall of the first doped well.
9. 9 . The semiconductor structure of claim 1 , wherein: the third doped well has a first racetrack structure, and the second doped well has a second racetrack structure disposed inside the first racetrack structure.
10. 10 . The semiconductor structure of claim 9 , wherein: the deep doped well has a third racetrack structure, and the fourth doped region has a fourth racetrack structure embedded in the first racetrack structure.
11. 11 . A semiconductor structure, comprising: an anode; a cathode adjacent the anode; and a first parasitic bipolar transistor connecting the anode to the cathode, wherein the anode comprises a first doped well doped with a first impurity having a first conductivity type, the cathode comprises a second doped well adjacent the first doped well and doped with a second impurity having a second conductivity type opposite the first conductivity type, and the first parasitic bipolar transistor comprises: a third doped region in the first doped well and doped with a third impurity having the second conductivity type; and a deep doped well doped with a fourth impurity having the first conductivity type under the first doped well, under the third doped region, and under the second doped well.
12. 12 . The semiconductor structure of claim 11 , comprising: a buried well doped with a fifth impurity having the second conductivity type under a portion of the deep doped well and under a portion of the second doped well.
13. 13 . The semiconductor structure of claim 11 , comprising: a second parasitic bipolar transistor connecting the anode to the cathode.
14. 14 . The semiconductor structure of claim 13 , wherein: the second parasitic bipolar transistor comprises: the deep doped well; and a fourth doped region adjacent the first doped well and the deep doped well and doped with a fifth impurity having the second conductivity type.
15. 15 . A method of forming a semiconductor structure, comprising: forming a first doped well doped with a first impurity having a first conductivity type in a semiconductor layer, wherein forming the first doped well comprises forming a first racetrack structure; forming a second doped well adjacent the first doped well and doped with a second impurity having a second conductivity type opposite the first conductivity type in the semiconductor layer, wherein forming the second doped well comprises forming a second racetrack structure inside the first racetrack structure; forming a third doped well doped with a third impurity having the first conductivity type connecting the first doped well and the second doped well, wherein forming the third doped well comprises forming a third racetrack structure under the first doped well and under a portion of the second doped well; and forming a fourth doped region doped with a fourth impurity having the second conductivity type in the first doped well and contacting the third doped well, wherein forming the fourth doped region comprises forming a fourth racetrack structure embedded in the first racetrack structure.
16. 16 . The method of claim 15 , comprising: forming a fifth doped well doped with a fifth impurity having the second conductivity type under a second portion of the second doped well and under a portion of the fourth doped region.
17. 17 . The method of claim 16 , comprising: forming a blocking layer doped with a sixth impurity having the first conductivity type adjacent the fifth doped well and under the first doped well.
18. 18 . The method of claim 15 , comprising: forming a fifth doped region doped with a fifth impurity having the second conductivity type adjacent the first doped well and adjacent the third doped well.
19. 19 . The method of claim 15 , comprising: forming an island structure doped with a fifth impurity having the first conductivity type inside the second racetrack structure.
20. 20 . The method of claim 15 , comprising: forming a first contact contacting the first doped well; forming a second contact contacting the second doped well; forming a third contact contacting the fourth doped region; and forming a conductive line connecting the first contact and the third contact.

Description

BACKGROUND An electro-static discharge (ESD) event is a sudden and unexpected voltage or current that transfers energy to a device. ESD events are known to render a device less operable than desired or inoperable altogether. Semiconductor structures include ESD protection devices to reduce the likelihood of damage from ESD events. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-11 are illustrations of a semiconductor structure at various stages of fabrication, in accordance with some embodiments. FIGS. 12-16 are illustrations of a semiconductor structure at various stages of fabrication, in accordance with some embodiments. FIGS. 17 and 18 are illustrations of a semiconductor structure, in accordance with some embodiments. FIG. 19 is a top view of a semiconductor structure, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and structures are described below to simplify the present disclosure. These are, of course, merely examples and are not intended limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for case of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The present application relates to a semiconductor structure and a method for fabricating a semiconductor structure. In accordance with some embodiments, a device, such as an electro-static discharge (ESD) protection device, is formed by forming an anode comprising a first doped well in a semiconductor layer and forming a cathode comprising a second doped well in the semiconductor layer counter-doped with respect to the first doped well. A deep doped well is formed under the first doped well and the second doped well. A counter-doped well is formed in the first doped well. The counter-doped well, the deep doped well, and the second doped well define a parasitic bipolar junction transistor in parallel with the anode and the cathode. The parasitic bipolar junction transistor increases the allowable current load of the ESD device and increases the human body mode (HBM) voltage. FIGS. 1-11 illustrate a semiconductor structure 100 at various stages of fabrication, in accordance with some embodiments. Referring to FIG. 1, a buried well 105 is formed in a semiconductor layer 110, in accordance with some embodiments. In some embodiments, the semiconductor layer 110 is part of a substrate comprising at least one of an epitaxial layer, a single crystalline semiconductor material such as, but not limited to, at least one of Si, Ge, SiGe, InGaAs, GaAs, InSb, GaP, GaSb, InAlAs, GaSbP, GaAsSb, or InP, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the semiconductor layer 110 comprises at least one of crystalline silicon or other suitable materials. The semiconductor layer 110 may be doped with a P-type impurity, such as at least one of boron, BF2, or other suitable p-type impurities. Other structures and/or configurations of the semiconductor layer 110 are within the scope of the present disclosure. The buried well 105 is formed to have an opposite conductivity type compared to that of the semiconductor layer 110. In some embodiments, the buried well 105 is doped with an N-type impurity, such as at least one of phosphorous, arsenic, or other suitable n-type impurities, since the semiconductor layer 110 is doped with a P-type impurity