US-12628436-B2 - Heterojunction cell and method for preparing same

US12628436B2US 12628436 B2US12628436 B2US 12628436B2US-12628436-B2

Abstract

A heterojunction cell and a method for preparing same. The heterojunction cell comprises: a semiconductor substrate layer; and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on the surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises: a bottom intrinsic layer; and a wide-band-gap intrinsic layer, which is located on the surface of the side of the bottom intrinsic layer that is away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer being greater than the band gap of the bottom intrinsic layer. The band gap of a wide-band-gap intrinsic layer is larger, and when sunlight irradiates a heterojunction cell, photons, the energy of which is less than that of the band gap of the wide-band-gap intrinsic layer, cannot be subjected to parasitic absorption.

Inventors

Xiaohua Xu
Ke XIN
Su Zhou
Daoren GONG
Wenjing Wang
Chen Li
Mengying Chen
Shangzhi CHENG

Assignees

Anhui Huasun Energy Co., Ltd.

Dates

Publication Date: 20260512
Application Date: 20220624
Priority Date: 20210707

Claims (15)

1 . A heterojunction cell, wherein the heterojunction cell comprises a semiconductor substrate layer; and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on a surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises a bottom intrinsic layer; and a wide-band-gap intrinsic layer located on the surface of the side of the bottom intrinsic layer facing away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer is greater than that of the bottom intrinsic layer; the wide-band-gap intrinsic layer comprises a first sub-wide-band-gap intrinsic layer to an Nth sub-wide-band-gap intrinsic layer, and N is an integer greater than or equal to 2; a kth sub-wide-band-gap intrinsic layer is located between the k+1th sub-wide-band-gap intrinsic layer and the semiconductor substrate layer; k is an integer greater than or equal to 1 and less than or equal to N−1; for the intrinsic semiconductor composite layer located on a front side of the semiconductor substrate layer, a refractive index of the k+1th sub-wide-band-gap intrinsic layer in the intrinsic semiconductor composite layer is smaller than that of the kth sub-wide-band-gap intrinsic layer.
2 . The heterojunction cell of claim 1 , wherein the intrinsic semiconductor composite layer is only located on the front side of the semiconductor substrate layer; or, the intrinsic semiconductor composite layer is only located on the back side of the semiconductor substrate layer; or, the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer.
3 . The heterojunction cell of claim 2 , wherein a material of the nth sub-wide-band-gap intrinsic layer comprises oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N.
4 . The heterojunction cell of claim 3 , wherein N is equal to 2.5.
5 . The heterojunction cell of claim 1 , wherein N is equal to 2, and the wide-band-gap intrinsic layer has a band gap ranging from 2.0 eV to 9 eV; a ratio of a thickness of the wide-band-gap intrinsic layer to the thickness of the bottom intrinsic layer is in a range from 1:1 to 3:1; and the wide-band-gap intrinsic layer has a thickness ranging from 2 nm to 8 nm, and the bottom intrinsic layer has a thickness ranging from 1.3 nm to 3.3 nm.
6 . The heterojunction cell of claim 2 , wherein the bottom intrinsic layer comprises a first sub-bottom intrinsic layer; a second sub-bottom intrinsic layer located on the surface of the side of a first sub-bottom intrinsic layer facing away from the semiconductor substrate layer; the defect state density of the second sub-bottom intrinsic layer is smaller than that of the first sub-bottom intrinsic layer.
7 . The heterojunction cell of claim 6 , wherein a ratio of a thickness of the first sub-bottom intrinsic layer to a thickness of the second sub-bottom intrinsic layer is in a range from 0.15:1 to 0.35:1.
8 . The heterojunction cell of claim 7 , wherein the first sub-bottom intrinsic layer has a thickness ranging from 0.3 nm to 0.8 nm, and the second sub-bottom intrinsic layer has a thickness ranging from 1 nm to 2.5 nm.
9 . The heterojunction cell of claim 2 , wherein a total thickness of the intrinsic semiconductor composite layer located on one side of the semiconductor substrate layer is in a range from 2 nm to 10 nm.
10 . The heterojunction cell of claim 2 , wherein the material of the first sub-wide-band-gap intrinsic layer comprises oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the material of a second sub-wide-band-gap intrinsic layer comprises carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, a molar ratio of oxygen to silicon in the first sub-wide-band-gap intrinsic layer is in a range from 1:1 to 1:5.
11 . The heterojunction cell of claim 3 , wherein the first sub-wide-band-gap intrinsic layer has a band gap ranging from 2.0 eV to 9 eV, and the second sub-wide-band-gap intrinsic layer has a band gap ranging from 2.0 eV to 9 eV.
12 . The heterojunction cell of claim 3 , wherein the material of the first sub-wide-band-gap intrinsic layer comprises carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, and the material of the second sub-wide-band-gap intrinsic layer comprises oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, a molar ratio of carbon to silicon in the first sub-wide-band-gap intrinsic layer is in a range from 1:1 to 1:5, and a molar ratio of oxygen to silicon in the second sub-wide-band-gap intrinsic layer is in a range from 1:1 to 1:5.
13 . The heterojunction cell of claim 3 , wherein a ratio of a thickness of the second sub-wide-band-gap intrinsic layer to the thickness of the first sub-wide-band-gap intrinsic layer is in a range from 0.5:1 to 1.5:1; a ratio of a thickness of the first sub-wide-band-gap intrinsic layer to a thickness of the bottom intrinsic layer is in a range from 0.5:1 to 1.5:1.
14 . The heterojunction cell of claim 13 , wherein the second sub-wide-band-gap intrinsic layer has a thickness ranging from 1.5 nm to 4 nm; the first sub-wide-band-gap intrinsic layer has a thickness ranging from 1.5 nm to 4 nm, and the bottom intrinsic layer has a thickness ranging from 1.3 nm to 3.3 nm.
15 . The heterojunction cell of claim 3 , wherein for the intrinsic semiconductor composite layer located on the back side of the semiconductor substrate layer, a valence band difference between the intrinsic semiconductor composite layer and the semiconductor substrate layer is in a range from 0.6 eV to 7.9 eV.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application claims priority to Chinese Patent Application No. 202110767660.2, entitled “Heterojunction cell and method for preparing same”, and filed to the China National Intellectual Property Administration on Jul. 7, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present application relates to the field of solar cell manufacturing, in particular to a heterojunction cell and a preparation method thereof. BACKGROUND Solar cells are clean energy cells, and it widely used in life and production. Heterojunction cell is an important solar cell. The heterojunction (HeteroJunction with intrinsic Thin layer, HJT for short) structure is centered on an N-type monocrystalline silicon substrate, and both sides of the N-type monocrystalline silicon substrate are respectively provided with a P-type amorphous silicon layer and an N-type amorphous silicon layer. An intrinsic amorphous silicon layer is added between the P-type amorphous silicon layer and N-type amorphous silicon layer and the N-type monocrystalline silicon substrate. After adopting this process, the passivation characteristics of the substrate silicon wafer are changed, thereby improving the conversion efficiency of heterojunction cells and making heterojunction cells a highly competitive solar cell technology in the market. However, due to the parasitic absorption of sunlight by the intrinsic amorphous silicon layer itself, it will affect the conversion efficiency of the heterojunction cells, and the conversion efficiency of the heterojunction cells needs to be further improved. SUMMARY OF THE INVENTION Therefore, a technical problem to be solved by the present application is to overcome the problem that the conversion efficiency of the heterojunction cell needs to be further improved in the prior art, so as to provide a heterojunction cell and a preparation method thereof. The present application provides a heterojunction cell, comprising a semiconductor substrate layer and an intrinsic semiconductor composite layer, wherein the intrinsic semiconductor composite layer is located on the surface of at least one side of the semiconductor substrate layer, and the intrinsic semiconductor composite layer comprises a bottom intrinsic layer; and a wide-band-gap intrinsic layer located on the surface of the side of the bottom intrinsic layer facing away from the semiconductor substrate layer, the band gap of the wide-band-gap intrinsic layer is greater than that of the bottom intrinsic layer. Optionally, the intrinsic semiconductor composite layer is only located on the front side of the semiconductor substrate layer; or, the intrinsic semiconductor composite layer is only located on the back side of the semiconductor substrate layer; or, the intrinsic semiconductor composite layer is located on both sides of the semiconductor substrate layer. Optionally, the wide-band-gap intrinsic layer comprises a first sub-wide-band-gap intrinsic layer to an Nth sub-wide-band-gap intrinsic layer, and N is an integer greater than or equal to 1. Optionally, the material of the nth sub-wide-band-gap intrinsic layer comprises oxygen-doped amorphous silicon, carbon-doped amorphous silicon, oxygen-doped nanocrystalline silicon or carbon-doped nanocrystalline silicon; n is an integer greater than or equal to 1 and less than or equal to N. Optionally, the bottom intrinsic layer comprises a first sub-bottom intrinsic layer; and a second sub-bottom intrinsic layer located on the surface of the side of the first sub-bottom intrinsic layer facing away from the semiconductor substrate layer; the defect state density of the second sub-bottom intrinsic layer is smaller than that of the first sub-bottom intrinsic layer. Optionally, the ratio of a thickness of the first sub-bottom intrinsic layer to a thickness of the second sub-bottom intrinsic layer is in a range from 0.15:1 to 0.35:1; Optionally, the first sub-bottom intrinsic layer has a thickness ranging from 0.3 nm to 0.8 nm, and the second sub-bottom intrinsic layer has a thickness ranging from 1 nm to 2.5 nm; Optionally, the total thickness of the intrinsic semiconductor composite layer located on one side of the semiconductor substrate layer is in a range from 2 nm to 10 nm. Optionally, N is an integer greater than or equal to 2, and the kth sub-wide-band-gap intrinsic layer is located between the k+1th sub-wide-band-gap intrinsic layer and the semiconductor substrate layer; k is an integer greater than or equal to 1 and less than or equal to N−1. Optionally, N is equal to 2. Optionally, the material of the first sub-wide-band-gap intrinsic layer comprises oxygen-doped amorphous silicon or oxygen-doped nanocrystalline silicon, and the material of the second sub-wide-band-gap intrinsic layer comprises carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon, a molar ratio of oxygen to silicon in the first sub-wide-band-gap