US-12628447-B2 - Image sensor having low parasitic light sensitivity

Abstract

An image sensor comprising a plurality of pixels formed inside and on top of a semiconductor substrate, each pixel comprising: a photosensitive area formed in the semiconductor substrate; a storage area formed in the semiconductor substrate; and a first transistor of transfer between the photosensitive area and the storage area, wherein the first transfer transistor comprises a gate vertically extending in the semiconductor substrate, from a top surface of the semiconductor substrate, inside of an insulating trench delimiting the storage area.

Inventors

• Olivier SAXOD
• François Ayel

Assignees

• Commissariat à l'énergie atomique et aux énergies alternatives

Dates

Publication Date

20260512

Application Date

20210901

Priority Date

20200904

Claims (9)

1. 1 . Image sensor comprising a plurality of pixels formed inside and on top of a semiconductor substrate, each pixel comprising: a photosensitive area formed in the semiconductor substrate; a storage area formed in the semiconductor substrate; and a first transistor of transfer between the photosensitive area and the storage area, wherein the first transfer transistor comprises a gate vertically extending in the semiconductor substrate, from a top surface of the semiconductor substrate, inside of a capacitive insulating trench, comprising an electrically-conductive region electrically insulated from the semiconductor substrate, delimiting the storage area, the gate of the first transfer transistor of each pixel being electrically insulated from the semiconductor substrate and from the conductive region; wherein the capacitive insulating trench comprises, in top view, top and bottom horizontal portions, left-hand and right-hand vertical portions and an intermediate horizontal portion interposed between the top and bottom horizontal portions and extending from the right-hand vertical portion towards the left-hand vertical portion, the first transistor of transfer comprising a portion formed at an angle of the capacitive insulating trench where the left-hand vertical portion and the top horizontal portion intersect, and another portion formed at an end of the intermediate horizontal portion located opposite the left-hand vertical portion; wherein the intermediate horizontal portion is parallel to the top horizontal portion and separated from the top horizontal portion by a distance in the range from 50 nm to 400 nm.
2. 2 . Sensor according to claim 1 , wherein: the conductive region is intended to be taken to a fixed potential; and the gate is intended to be taken to a variable potential, having a first level controlling the setting to the on state of the first transfer transistor and a second level controlling the setting to the off state of the first transfer transistor.
3. 3 . Sensor according to claim 1 , wherein the gate is made of a metal or of a metal alloy.
4. 4 . Sensor according to claim 1 , wherein the gate is made of polysilicon.
5. 5 . Sensor according to claim 1 , configured to estimate distances by time of flight.
6. 6 . Sensor according to claim 1 , wherein the storage area is separated from the first transfer transistor by a second transfer transistor.
7. 7 . Sensor according to claim 6 , wherein the second transfer transistor comprises a gate vertically extending in the semiconductor substrate, from the top surface of the semiconductor substrate, inside an insulating trench delimiting the storage area.
8. 8 . Method of controlling a sensor according to claim 6 comprising, for each pixel, the steps of: a) setting the second transfer transistor to the on state; b) setting the first transfer transistor to the on state; c) after steps a) and b), setting the first transfer transistor to the off state; and d) after step c), setting the second transfer transistor to the off state.
9. 9 . Method according to claim 8 , wherein steps a), and b) are carried out simultaneously.

Description

CROSS REFERENCE TO RELATED APPLICATION(S) This application is a translation of and claims the priority benefit of French patent application number 20/08983, filed on Sep. 4, 2020, entitled “Capteur d'images” which is hereby incorporated by reference to the maximum extent allowable by law. TECHNICAL BACKGROUND The present disclosure generally concerns electronic devices and, more specifically, image sensors. PRIOR ART Images sensors, for example, of the type described in patent application US2019086519, having their pixels comprising a photosensitive area, or detection area, separate from at least one storage area by a transfer transistor, are known. SUMMARY There is a need to improve existing image sensors. It would in particular be desirable to obtain image sensors having a low parasitic light sensitivity (PLS). An embodiment overcomes all or part of the disadvantages of known image sensors. An embodiment provides an image sensor comprising a plurality of pixels formed inside and on top of a semiconductor substrate, each pixel comprising: a photosensitive area formed in the semiconductor substrate;a storage area formed in the semiconductor substrate; anda first transistor of transfer between the photosensitive area and the storage area, wherein the first transfer transistor comprises a gate vertically extending in the semiconductor substrate, from a top surface of the semiconductor substrate, inside of an insulating trench delimiting the storage area. According to an embodiment, the insulating trench is a capacitive insulating trench comprising a metal region electrically insulated from the semiconductor substrate. According to an embodiment, the gate of the first transfer transistor of each pixel is electrically insulated from the semiconductor substrate and from the metal region. According to an embodiment: the metal region is intended to be taken to a fixed potential; andthe gate is intended to be taken to a variable potential, having a first level controlling the setting to the on state of the first transfer transistor and a second level controlling the setting to the off state of the first transfer transistor. According to an embodiment, the gate is made of a metal or of a metal alloy. According to an embodiment, the gate is made of polysilicon. According to an embodiment, the sensor is configured to estimate distances by time of flight. According to an embodiment, the storage area is separated from the first transfer transistor by a second transfer transistor. According to an embodiment, the second transfer transistor comprises a gate vertically extending in the semiconductor substrate, from the top surface of the semiconductor substrate, inside of the insulating trench delimiting the storage area. An embodiment provides a method of controlling a sensor such as described, the method comprising, for each pixel, the steps of: a) setting the second transfer transistor to the on state; b) setting the first transfer transistor to the on state; c) after steps a) and b), setting the first transfer transistor to the off state; and d) after step c), setting the second transfer transistor to the off state. According to an embodiment, steps a) and b) are carried out simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments and implementation modes in connection with the accompanying drawings, in which: FIG. 1 is a partial simplified top view of an image sensor pixel according to a first embodiment; FIG. 2 is a partial simplified cross-section view of the pixel of FIG. 1 along plane AA of FIG. 1; FIG. 3 is a partial simplified cross-section view of a variant of the pixel of FIG. 1 along plane AA of FIG. 1; FIG. 4 is a graph illustrating a step of a pixel control method according to a first implementation mode; FIG. 5 is a graph illustrating another step of the pixel control method according to the first implementation mode; FIG. 6 is a graph illustrating still another step of the pixel control method according to the first implementation mode; FIG. 7 is a partial simplified top view of another variant of the pixel of FIG. 1; FIG. 8 is a partial simplified top view of still another variant of the pixel of FIG. 1; FIG. 9 is a partial simplified top view of still another variant of the pixel of FIG. 1; FIG. 10 is a partial simplified top view of two pixels of the type of that discussed in relation with FIG. 9; FIG. 11 is a partial simplified top view of two pixels of the type of that discussed in relation with FIG. 7; FIG. 12 is a partial simplified top view of still another variant of the pixel of FIG. 1; FIG. 13 is a partial simplified top view of still another variant of the pixel of FIG. 1; FIG. 14 is a partial simplified top view of two pixels of the type of that discussed in relation with FIG. 13; FIG. 15 is a partial simplified top view of a variant of